A review of fault-tolerant techniques for the enhancement of integrated circuit yield

This paper examines the ways in which the yield of integrated circuit production can be improved through the use of circuit design techniques. The bulk of the paper is concerned with fault-tolerant approaches but aspects of circuit layout are also considered briefly. The paper reviews the fault-tolerant techniques which are currently in use in memory chips and discusses those which have been proposed for other architectures and large-area chips up to whole wafers. It surveys the crucial topics of yield prediction and of repair technology and outlines the options available for the future.

[1]  J. Yamada,et al.  Submicron VLSI memory circuits , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  W. R. Moore,et al.  Fault-tolerant communications for wafer-scale integration of a processor array , 1985 .

[3]  Dwight L. Crook,et al.  Redundancy Reliability , 1981, 19th International Reliability Physics Symposium.

[4]  T. Yanagawa.  Yield degradation of integrated circuits due to spot defects , 1972 .

[5]  Charles H. Stapper.  Yield Model for Fault Clusters Within Integrated Circuits , 1984, IBM J. Res. Dev..

[6]  T. Kondoh,et al.  A 17ns 64K CMOS RAM with a schmitt trigger sense amplifier , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[7]  G. Atwood,et al.  A NMOS 64K static RAM , 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[8]  J. B. Angell,et al.  Redundancy for LSI Yield Enhancement , 1967 .

[9]  T. Masuhara,et al.  A Hi-CMOSII 8Kx8 bit static RAM , 1982, IEEE Journal of Solid-State Circuits.

[10]  S. E. Schuster.  Multiple word/bit line redundancy for semiconductor memories , 1978 .

[11]  S. M. Hu,et al.  Some considerations in the formulation of IC yield statistics , 1979 .

[12]  A. Sengupta,et al.  Realization of Fault-Tolerant Machines—Linear Code Application , 1981, IEEE Transactions on Computers.

[13]  H. Davis.  A word-wide 1Mb ROM with error correction , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[14]  R.C. Aubusson,et al.  Wafer-scale integration-a fault-tolerant procedure , 1978, IEEE Journal of Solid-State Circuits.

[15]  H. Momose,et al.  A 28ns CMOS SRAM with bipolar sense amplifiers , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[16]  R.D. Rung.  Determining IC layout rules for cost minimization , 1981, IEEE Journal of Solid-State Circuits.

[17]  T. Awaya,et al.  64Kb ECL RAM with redundancy , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[18]  R. M. Lea,et al.  WSI Distributed Logic Memories , 1979 .

[19]  L. P. McNamee,et al.  A means of reducing custom LSI interconnection requirements , 1972 .

[20]  S. Shinozaki,et al.  A 1Mb CMOS DRAM with fast page and static column modes , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[21]  T.E. Mangir.  Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part II—Restructurable interconnects for RVLSI and WSI , 1984, Proceedings of the IEEE.

[22]  J.R. Yeargain,et al.  An 80 ns 32K EEPROM using the FETMOS cell , 1982, IEEE Journal of Solid-State Circuits.

[23]  J. Petrizzi,et al.  A 1Mb CMOS DRAM , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[24]  S. Kohyama,et al.  A low power resistive load 64 kbit CMOS RAM , 1982, IEEE Journal of Solid-State Circuits.

[25]  R. Taylor,et al.  A 1Mb CMOS DRAM with a divided bitline matrix architecture , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[26]  Charles E. Leiserson,et al.  How to assemble tree machines , 1984 .

[27]  C. H. Stapper.  Comments on “some considerations in the formulation of IC yield statistics” , 1981 .

[28]  W R Moore,et al.  Testability of a VLSI Systolic Array , 1985, ESSCIRC '85: 11th European Solid-State Circuits Conference.

[29]  R. G. Nelson,et al.  Laser programmable redundancy and yield improvement in a 64K DRAM , 1981 .

[30]  Yves Crouzet,et al.  Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability , 1980, IEEE Transactions on Computers.

[31]  J. Schutz,et al.  A 70ns high density CMOS DRAM , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[32]  Vishwani D. Agrawal,et al.  Characterizing the LSI Yield Equation from Wafer Test Data , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[33]  R. Houghton,et al.  A 72Kb bipolar DRAM , 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[34]  B. Fitzgerald,et al.  A 288Kb dynamic RAM , 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[35]  RODGER A. CLIFF,et al.  Acceptable Testing of VLSI Components Which Contain Error Correctors , 1980, IEEE Transactions on Computers.

[36]  T. Mano,et al.  A 256K dynamic MOS RAM with alpha immune and redundancy , 1982 .

[37]  Mariagiovanna Sami,et al.  Reconfigurable architectures for VLSI processing arrays , 1983, Proceedings of the IEEE.

[38]  K.C. Hardee,et al.  A fault-tolerant 30 ns/375 mW 16Kx1 NMOS static RAM , 1981, IEEE Journal of Solid-State Circuits.

[39]  E. A. Sack,et al.  Evolution of the concept of a computer on a slice , 1964 .

[40]  Vishwani D. Agrawal.  Comments on "An Approach to Highly Integrated Computer-Maintained Cellular Arrays" , 1979, IEEE Trans. Computers.

[41]  Masahiko Oka,et al.  A Defect-Tolerant Design for Full-Wafer Memory LSI , 1983, ESSCIRC '83: Ninth European Solid-State Circuits Conference.

[42]  James B. Angell,et al.  Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.

[43]  T. Wada,et al.  A 1-Mbit full-wafer MOS RAM , 1980, IEEE Transactions on Electron Devices.

[44]  Tetsuya Iizuka,et al.  A programmable 80ns 1Mb CMOS EPROM , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[45]  I. Masuda,et al.  A fault tolerant MOS-LSI for train controller applications , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[46]  Horst Barsuhn.  Functional Wafer - A New Step in LSI , 1977, ESSCIRC '77: 3rd European Solid State Circuits Conference.

[47]  Y. Hsia,et al.  ADAPTIVE WAFER SCALE INTEGRATION , 1979 .

[48]  J. Bernard.  The IC yield problem: A tentative analysis for MOS/SOS circuits , 1978, IEEE Transactions on Electron Devices.

[49]  Lawrence Snyder,et al.  Wafer scale integration of Configurable, Highly Parallel (CHiP) processors , 1982, International Conference on Parallel Processing.

[50]  Frank Thomson Leighton,et al.  Wafer-scale integration of systolic arrays , 1982, 23rd Annual Symposium on Foundations of Computer Science (sfcs 1982).

[51]  Arnold L. Rosenberg,et al.  The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors , 1983, IEEE Transactions on Computers.

[52]  M. Holler,et al.  A 100ns 256K CMOS EPROM , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[53]  B. F. Fitzgerald,et al.  Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement , 1980, IBM J. Res. Dev..

[54]  H. Stopper.  A wafer with electrically programmable interconnections , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[55]  Algirdas Avizienis,et al.  Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs , 1982, IEEE Transactions on Computers.

[56]  H. Kawamoto,et al.  A 1Mb ROM with on chip ECC for yield enhancement , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[57]  Frank Thomson Leighton,et al.  Wafer-Scale Integration of Systolic Arrays , 1985, IEEE Trans. Computers.

[58]  Richard L. Petritz.  Current Status of Large Scale Integration Technology , 1967 .

[59]  Renato Stefanelli,et al.  Reconfigurable architectures for VLSl processing arrays , 1899 .

[60]  H. Kikuchi,et al.  A 4-Mbit Full-Wafer ROM , 1980, IEEE Journal of Solid-State Circuits.

[61]  R. Kertis,et al.  A 59ns 256K DRAM using LD3technology and double level metal , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[62]  J. W. Lathrop,et al.  Yield analysis of large integrated-circuit chips , 1972 .

[63]  R. Schnadt,et al.  FET RAMs , 1979, 1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[64]  T.P. Haraszti.  A novel associative approach for fault-tolerant MOS RAMs , 1982, IEEE Journal of Solid-State Circuits.

[65]  Israel Koren,et al.  Embedding Tree Structures in VLSI Hexagonal Arrays , 1984, IEEE Transactions on Computers.

[66]  David W. Greve.  Programming mechanism of polysilicon resistor fuses , 1982 .

[67]  B. T. Murphy,et al.  Cost-size optima of monolithic integrated circuits , 1964 .

[68]  P.W. Wyatt,et al.  A Wafer-Scale Digital Integrator Using Restructurable VSLI , 1985, IEEE Journal of Solid-State Circuits.

[69]  B. Venkatesh,et al.  512K EPROMs , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[70]  Frank B. Manning,et al.  An Approach to Highly Integrated, Computer-Maintained Cellular Arrays , 1977, IEEE Transactions on Computers.

[71]  Fumio Horiguchi,et al.  A 1Mb DRAM with a folded capacitor cell structure , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[72]  A. Mohsen,et al.  A 80ns 64K DRAM , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[73]  R. Heckelman,et al.  Self-testing VLSI , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[74]  C.H. Stapper,et al.  Integrated circuit yield statistics , 1983, Proceedings of the IEEE.

[75]  T. Nakano,et al.  A sub 100ns 256Kb DRAM , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[76]  H. T. Kung,et al.  Wafer-scale integration and two-level pipelined implementations of systolic arrays , 1984, J. Parallel Distributed Comput..

[77]  P. Sharp,et al.  Redundancy techniques for fast static RAMs , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[78]  T. Rodgers.  Redundancy in RAMs , 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[79]  J. Schutz,et al.  A sub 100ns 256K DRAM in CMOS III technology , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[80]  V. McKenny.  A 5V 64K EPROM utilizing redundant circuitry , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[81]  C. H. Stapper,et al.  Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product , 1980, IBM J. Res. Dev..

[82]  F. I. Osman.  Error-correction technique for random-access memories , 1982 .

[83]  Kazuyasu Fujishima,et al.  A 90ns 1Mb DRAM with multi-bit test mode , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[84]  William Eccleston,et al.  Spatial distribution of defects in SiO2 , 1978 .

[85]  K. Shirai,et al.  A 150ns 288k CMOS EPROM with redundancy , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[86]  M. Embrathiry,et al.  Triple poly II DRAM memory cell , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[87]  O. Paz,et al.  Modification of Poisson statistics: modeling defects induced by diffusion , 1977 .

[88]  Donald S. Fussell,et al.  Fault-tolerant wafer-scale architectures for VLSI , 1982, ISCA 1982.

[89]  Danny Cohen,et al.  VLSI System for SAR Processing , 1979 .

[90]  A. Folmsbee,et al.  A 128K EPROM with redundancy , 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[91]  Charles H. Stapper,et al.  Modeling of Defects in Integrated Circuit Photolithographic Patterns , 1984, IBM J. Res. Dev..

[92]  Daniel P. Siewiorek,et al.  Workshop Report: Fault-Tolerant VLSI Design , 1980, Computer.

[93]  R.P. Cenker,et al.  A fault-tolerant 64K dynamic random-access memory , 1979, IEEE Transactions on Electron Devices.

[94]  Paul Lowy,et al.  Techniques for improving engineering productivity of VLSI designs , 1981 .

[95]  S. Kohyama,et al.  Fault tolerant 92160 bit multiphase CCD memory , 1977, 1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[96]  S. Kohyama,et al.  An ultralow power 8Kx8-bit full CMOS RAM with a six-transistor cell , 1982, IEEE Journal of Solid-State Circuits.

[97]  T. Yanagawa,et al.  Influence of epitaxial mounds on the yield of integrated circuits , 1969 .

[98]  A. C. Dumbri,et al.  A 256K dynamic random access memory , 1982, IEEE Journal of Solid-State Circuits.

[99]  M. J. Day,et al.  Yield-enhancement of a large systolic array chip , 1984 .

[100]  Hubert H. Love,et al.  The Associative Linear Array Processor , 1977, IEEE Transactions on Computers.

[101]  T. Masuhara,et al.  A high-speed Hi-CMOSII 4K static RAM , 1981, IEEE Journal of Solid-State Circuits.

[102]  J. W. Lathrop,et al.  A discretionary wiring system as the interface between design automation and semiconductor array manufacture , 1967 .

[103]  Eugen I. Muehldorf,et al.  LSI logic testing — An overview , 1981, IEEE Transactions on Computers.

[104]  M. Yamada,et al.  A 70ns 256K DRAM with bitline shielding structure , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[105]  Yves Crouzet,et al.  Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor , 1980, IEEE Transactions on Computers.

[106]  J. Sredni.  Use of power transformations to model the yield of IC's as a function of active circuit area , 1975, 1975 International Electron Devices Meeting.

[107]  Donald S. Fussell,et al.  DESIGNING SYSTOLIC ALGORITHMS FOR FAULT-TOLERANCE. , 1984 .

[108]  Myron J. Rand.  Reliability of LSI Memory Circuits Exposed to Laser Cutting , 1979, 17th International Reliability Physics Symposium.

[109]  I. M. Mackintosh,et al.  Programmed interconnections—A release from tyranny , 1964 .

[110]  R. Bender,et al.  A 256K DRAM with descrambled redundancy test capability , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[111]  T.E. Mangir,et al.  Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI , 1984, Proceedings of the IEEE.

[112]  D. Wooten,et al.  A 5V-only EEPROM with internal program/erase control , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[113]  M. Wada,et al.  A redundancy circuit for a fault-tolerant 256K MOS RAM , 1982, IEEE Journal of Solid-State Circuits.