A novel test structure to monitor electromigration

Elect romigration continues to be one of the important failure mechanisms limiting the attainment of higher levels of reliability in sub-micron geometry VLSI circuits. Successful management of elect romigration in future requires adoption of effective statistical process control techniques, in addition to the traditional quality control tests and inspections. The aim of this project was to develop a test structure and test methodology to monitor elect romigration for metallisation process control. Based on analysis and some preliminary measurements on chequerboards, a new test structure and methodology was proposed to monitor electromigration. 'Chequerboards' are dense patterns of clear and opaque squares of metal film over silicon. As part of this study, an electromigration test chip was designed. It consists of two designs: The design EU9 101 mainly contains chequerboards while EU9 102 contains conventional and other elect romigration test structures for comparative assessment. The chip design, fabrication and measurement details including the instrumentation aspects are also given in the thesis. One of the key process parameters, namely, linewidth is chosen to demonstrate the sensitivity of the proposed methodology to monitor elect romigrat ion. Possible applications of the new structure in electromigration measurements, other than process monitoring are also discussed. The thesis also contains a review of the elect romigration measurement techniques, some measurements using the conventional test structure and a detailed discussion on the limits of conventional tests.