A novel oscillation-based BIST for ADCs

An oscillation based BIST scheme for ADCs was proposed. A novel technique was used to timing output codes of ADCs by digital mode. In the BIST structure, the test signal was controlled by the feedback circuit to oscillate between two transition edges of ADCs. The rising and falling time of the test signal during oscillation period was in direct proportion to the code width of ADCs under testing. By timing the rising or falling time and comparing it with an ideal time, the offset error, differential non-linearity (DNL), integral non-linearity (INL) and gain error can be achieved.

[1]  Karim Arabi,et al.  Parametric and catastrophic fault coverage of analog circuits in oscillation-test methodology , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[2]  Bozena Kaminska,et al.  Oscillation built-in self test (OBIST) scheme for functional and structural testing of analog and mixed-signal integrated circuits , 1997, Proceedings International Test Conference 1997.

[3]  Florence Azaïs,et al.  Implementation of a linear histogram BIST for ADCs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[4]  D. De Venuto.  Review of Test Strategies and Resources used in High-Resolution Interface Testing , 2002 .

[5]  Sungho Kang,et al.  Code-width testing-based compact ADC BIST circuit , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Michel Renovell,et al.  Towards an ADC BIST scheme using the histogram test technique , 2000, Proceedings IEEE European Test Workshop.