A novel NMR structure with concurrent output error location capability

This paper proposes a novel N-modular redundancy (NMR) structure with concurrent output error location (COEL) capability. The concurrent output error locatable NMR structure consists of a conventional NMR structure and a totally self-checking (TSC) extra circuit with N+1 two-rail code outputs. This extra circuit is used for locating the output error produced by any replicated module or the voter, and the internal fault produced by the extra circuit itself. Such a self-checking extra circuit is called the output error locator (OEL). It is constructed by conventional TSC two-rail code checkers (TRCs) and self-testing multi-input comparators. Each comparator is made by adding one extra two-rail code input to the cascaded multi-input comparator. The error handling capabilities, hardware complexity and propagation delay are analyzed for the proposed OEL. The performance of the proposed scheme and that of the Gaitanis's scheme are compared for a triple modular redundancy (TMR) structure.

[1]  Eiji Fujiwara,et al.  A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing , 1987, IEEE Transactions on Computers.

[2]  Charles E. Stroud,et al.  Design for testability and test generation for static redundancy system level fault-tolerant circuits , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[3]  Nikolaos Gaitanis.  The Design of Totally Self-Checking TMR Fault-Tolerant Systems , 1988, IEEE Trans. Computers.

[4]  Ronald C. de Vries,et al.  Design of Self-Checking Iterative Networks , 1988, IEEE Trans. Computers.

[5]  Nikolaos Gaitanis.  A Totally Self-Checking Error Indicator , 1985, IEEE Transactions on Computers.

[6]  Michael Nicolaidis,et al.  Self-exercising checkers for unified built-in self-test (UBIST) , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  John P. Hayes,et al.  Design of Totally Fault Locatable Combinational Networks , 1980, IEEE Transactions on Computers.

[8]  Y. Min,et al.  Strongly fault secure PLAs and totally self-checking checkers , 1988 .

[9]  Michael Nicolaidis.  Fail-Safe Interfaces for VLSI: Theoretical Foundations and Implementation , 1998, IEEE Trans. Computers.

[10]  Anthony S. Wojcik,et al.  A General, Constructive Approach to Fault-Tolerant Design Using Redundancy , 1989, IEEE Trans. Computers.

[11]  TAKASHI NANYA,et al.  On Error Indication for Totally Self-Checking Systems , 1987, IEEE Transactions on Computers.

[12]  C. V. Ramamoorthy,et al.  Reliability Analysis of Systems with Concurrent Error Detection , 1975, IEEE Transactions on Computers.