sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing
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[1] Rob A. Rutenbar,et al. FPGA routing and routability estimation via Boolean satisfiability , 1997, FPGA '97.
[2] Randal E. Bryant,et al. Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[3] Randal E. Bryant,et al. Efficient implementation of a BDD package , 1991, DAC '90.
[4] R. Bryant. Binary decision diagrams and beyond: enabling technologies for formal verification , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[5] Robert K. Brayton,et al. Sequential circuit design using synthesis and optimization , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.
[6] Gi-Joon Nam,et al. A boolean-based layout approach and its application to fpga routing , 2001 .
[7] Rob A. Rutenbar,et al. A comparative study of two Boolean formulations of FPGA detailed routing constraints , 2001, IEEE Transactions on Computers.
[8] Bernd Becker,et al. Exact switchbox routing with search space reduction , 2000, ISPD '00.
[9] R. Rudell. Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD 1993.
[10] Bart Selman,et al. Local search strategies for satisfiability testing , 1993, Cliques, Coloring, and Satisfiability.
[11] Rob A. Rutenbar,et al. A comparative study of two Boolean formulations of FPGA detailed routing constraints , 2001, ISPD '01.
[12] Sharad Malik,et al. Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[13] Byungki Cha,et al. Local Search Algorithms for Partial MAXSAT , 1997, AAAI/IAAI.
[14] Rob A. Rutenbar,et al. A Boolean satisfiability-based incremental rerouting approach with application to FPGAs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[15] Joao Marques-Silva. Algorithms for Satisfiability in Combinational Circuits Based on Backtrack Search and Recursive Learning , 1999 .
[16] Randal E. Bryant,et al. Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.
[17] Wolfgang Kunz,et al. An exact algorithm for solving difficult detailed routing problems , 2001, ISPD '01.
[18] Srinivas Devadas,et al. Optimal layout via Boolean satisfiability , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[19] Shin-ichi Minato,et al. Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems , 1993, 30th ACM/IEEE Design Automation Conference.
[20] Olivier Coudert,et al. A Performance Study of BDD-Based Model Checking , 1998, FMCAD.
[21] Rob A. Rutenbar,et al. Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT , 1999, FPGA '99.
[22] R. I. Bahar,et al. Algebraic decision diagrams and their applications , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[23] Zohar Manna,et al. Differential BDDs , 1995, Computer Science Today.
[24] Randal E. Bryant,et al. Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW , 2001, DAC '01.
[25] Rob A. Rutenbar,et al. FPGA routing and routability estimation via Boolean satisfiability , 1998, IEEE Trans. Very Large Scale Integr. Syst..
[26] R. Rudell. Dynamic variable ordering for ordered binary decision diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[27] John N. Hooker,et al. Resolution and the integrality of satisfiability problems , 1996, Math. Program..
[28] J. P. Marques,et al. GRASP : A Search Algorithm for Propositional Satisfiability , 1999 .
[29] Hantao Zhang,et al. SATO: An Efficient Propositional Prover , 1997, CADE.