Testability profile estimation of VLSI circuits from fault coverage

The authors present a new method of estimating the testability profile of a circuit from its random fault coverage data. They have recently developed a relationship between fault coverage and testability profile. However, their testability profile estimates were based on unknown distribution of input vectors and used Bayes theorem with a priori uniform detection probability distribution. The testability profile is modeled as a series of impulse functions and the strength of each estimated from fault coverage data. Experimental results given on three of the large ISCAS benchmark circuits reflect the accuracy of these estimates. Applications include: coverage prediction from testability analysis, prediction of test length, and test generation by fault sampling.<<ETX>>