A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET

This 56Gb/s PAM-4 transceiver leverages the high logic density provided by the 7nm FinFET technology through rigorous application of digital design styles: An All-Digital PLL and SST transmitter are combined with a 28GS/s 8b ADC and DSP receiver, with the analog signal processing limited to a two stage front-end. The receiver achieves a raw 1e-7 BER with a-33dB insertion loss channel while consuming 500mW, including the 20-tap FFE and 1-tap DFE equipped DSP section.

[1]  Yusuf Leblebici,et al.  22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[2]  Shahaboddin Moazzeni,et al.  A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET , 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

[3]  Bo Zhang,et al.  3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[4]  Junho Cho,et al.  A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).