Submicron silicon bipolar master-slave D-type flip-flop for use as 8.1 Gbit/s decision circuit and 11.2 Gbit/s demultiplexer

We have designed and implemented a submicron silicon bipolar master-slave D-type flip-flop integrated circuit which can be used either as a decision circuit or a demultiplexer, operating at data rates as high as 8.1 and 11.2 Gbit/s, respectively. The circuit was fabricated using a 0.6 μm, nonpolysilicon emitter technology, occupying an area of 0.8 mm × 0.9 mm, and dissipating 410 mW of power.