LDPC Encoder Hardware Design for the Next Generation Wireless LAN

Abstract Encoder design of low density parity check codes(LDPC) is a crucial step for the next generation wireless LAN based on IEEE802.11ac. Each IP of LDPC encoder on the market needs to use storage check matrix and other units individually, which often can take up a lot of storage resources. This paper investigates the principle of RU coding and proposes an improved algorithm based on RU to further reduce complexity. At last we give the system framework of entire encoder, including the submatrix multiplication schematic diagram, codeword merger unit and LDPC encoder memory, which can provide important reference for ASIC or FPGA design.

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