A background fast convergence algorithm for timing skew in time-interleaved ADCs

Time-interleaved analog-to-digital converters (TI ADCs) suffer offset mismatch, gain mismatch, bandwidth mismatch and timing skew, of which timing skew degrades the performance most severely. In this paper, a background fast convergence calibration algorithm for timing skew is proposed. With known the range of input frequency, the algorithm employs the statistical property of the wrong digital outputs to estimate the sign of the timing skew. Then a correction module based on polynomial interpolation starts to compensate the wrong outputs. This algorithm has some merits of simplicity, fast convergence rate and feasible to implement. Behavioral simulation of an 8-bit 8-channel 3.2GS/s TI ADC reveals that with an input frequency of 0-1.4GHz, this algorithm is effective to improve the signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the TI ADC.

[1]  Peng Zhang,et al.  An 8 Bit 4 GS/s 120 mW CMOS ADC , 2013, IEEE Journal of Solid-State Circuits.

[2]  Marie-Minerve Louërat,et al.  Background analog and mixed signal calibration system for time-interleaved ADC , 2015, Microelectron. J..

[3]  Stephen H. Lewis,et al.  A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors , 2010, IEEE Journal of Solid-State Circuits.

[4]  Jingbo Wang,et al.  A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture , 2006, IEEE Journal of Solid-State Circuits.

[5]  Chun-Cheng Huang,et al.  A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques , 2011, IEEE Journal of Solid-State Circuits.

[6]  Bertrand Le Gal,et al.  A new orthogonal online digital calibration for time-interleaved analog-to-digital converters , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[7]  M El-Chammas,et al.  A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration , 2010, IEEE Journal of Solid-State Circuits.

[8]  Jun Shan Wang,et al.  Adaptive Calibration of Channel Mismatches in Time-Interleaved ADCs Based on Equivalent Signal Recombination , 2014, IEEE Transactions on Instrumentation and Measurement.

[9]  Chien-Cheng Tseng,et al.  Digital differentiator design using fractional delay filter and limit computation , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Yun Chiu,et al.  Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Unto K. Laine,et al.  Splitting the unit delay [FIR/all pass filters design] , 1996, IEEE Signal Process. Mag..

[12]  Unto K. Laine,et al.  Splitting the Unit Delay - Tools for fractional delay filter design , 1996 .

[13]  Qi Yu,et al.  A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[14]  Wenbo Liu,et al.  Time-Interleaved Analog-to-Digital Conversion With Online Adaptive Equalization , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  Anthony Chan Carusone,et al.  Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS , 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

[16]  Boris Murmann,et al.  General analysis on the impact of phase-skew in time-interleaved ADCs , 2009, 2008 IEEE International Symposium on Circuits and Systems.

[17]  Behzad Razavi,et al.  Design Considerations for Interleaved ADCs , 2013, IEEE Journal of Solid-State Circuits.