High-reliability, low-energy microarchitecture synthesis

Continuous scaling of device dimensions has accelerated the power dissipation and electromigration-induced reliability degradation in integrated circuits. Submicrometer scaling increases the fraction of on-chip energy dissipated on long interconnects and buses. In addition, submicrometer-level scaling increases current density in long interconnects and buses, causing structural damage in metal lines due to electromigration (a major failure phenomenon in integrated circuits). We present algorithms for synthesizing high-reliability, low-energy microarchitectures. This can be realized by judiciously binding and scheduling the data transfers of a control-data-flow graph representation of an application onto the buses in the microarchitecture. The algorithm considers (i) correlations between data transfers, (ii) constraints on the number of buses, and (iii) area and delay.

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