Automatic layout generation for CMOS operational amplifiers

An analog silicon compiler for CMOS op amps (OPASYN) has been developed. The synthesis system takes as inputs system-level specifications, fabrication-dependent technology parameters, and geometric layout rules. Based on the general domain of the specifications, the program first selects an appropriate circuit topology from a database and determines optimal values for the set of design parameters so as to meet the design objectives. Subsequently, a mask-level layout for the given circuit with its optimized device sizes is constructed using an approach based on a few leaf-cell generators and on circuit-dependent slicing trees that guarantee sound arrangements of the individual components. The synthesis process is fast enough for the program to be used interactively at the system-design level by system engineers who are inexperienced in op amp design.<<ETX>>