Optimization of Power and Area in Low-Noise CMOS Bio-Signal Amplifiers

Area and power consumption are the most important parameters in integrated bio-potential signal amplifier with low noise and low bandwidth requirements. In this paper we present an analytical method for optimizing differential amplifiers for a constant input-referred noise level. Power- area optimization is performed over 1mHz to 10kHz in a 0.18μm CMOS technology. The amplifier consumes 22μA from a 1.8V power supply and the total equivalent input-referred noise over that bandwidth is equal to 2.4μVrms. The results, validated by SPICE circuit simulations, indicate that the amplifier can be optimized for specific input-referred RMS noise level.

[1]  Y. Tsividis Operation and modeling of the MOS transistor , 1987 .

[2]  Amir M. Sodagar,et al.  Analysis and Design of Tunable Amplifiers for Implantable Neural Recording Applications , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[3]  J. M. Rochelle,et al.  Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design , 2006 .

[4]  Shahin Jafarabadi-Ashtiani,et al.  Optimizing power-area for constant input-referred noise level in MOSFETs , 2009, 2009 European Conference on Circuit Theory and Design.

[5]  E. Sanchez-Sinencio,et al.  Optimal design of low power nested GM-C compensation amplifiers using a current-based MOS transistor model , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[6]  Carlos Galup-Montoro,et al.  Sizing of MOS transistors for amplifier design , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[7]  R. R. Harrison,et al.  A low-power low-noise CMOS amplifier for neural recording applications , 2003, IEEE J. Solid State Circuits.

[8]  Reid R. Harrison,et al.  A Versatile Integrated Circuit for the Acquisition of Biopotentials , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[9]  Denis Flandre,et al.  Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology , 1997 .