Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.

[1]  Víctor H. Champac,et al.  Signal integrity verification using high speed monitors , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[2]  Marcel J. M. Pelgrom,et al.  A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[3]  Christopher M. Durham,et al.  High Speed CMOS Design Styles , 1998 .

[4]  J. Liu,et al.  Pseudo-Exhaustive Built-in Self-Testing of Signal Integrity for High-Speed SoC Interconnects , 2007, 2007 IEEE Instrumentation & Measurement Technology Conference IMTC 2007.

[5]  Jaume Segura,et al.  CMOS Electronics: How It Works, How It Fails , 2004 .

[6]  B. Krauter,et al.  Including inductive effects in interconnect timing analysis , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[7]  Niraj K. Jha,et al.  Interconnect-aware low-power high-level synthesis , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Mehrdad Nourani,et al.  Power-supply noise in SoCs: ATPG, estimation and control , 2005, IEEE International Conference on Test, 2005..

[9]  David J. Frank,et al.  Nanoscale CMOS , 1999, Proc. IEEE.

[10]  Mehrdad Nourani,et al.  Built-in self-test for signal integrity , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[11]  James D. Meindl,et al.  A physical alpha-power law MOSFET model , 1999 .

[12]  Mehrdad Nourani,et al.  Testing interconnects for noise and skew in gigahertz SoCs , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[13]  Matthew Mahoney,et al.  DSP-Based Testing of Analog and Mixed-Signal Circuits , 1987 .

[14]  David Blaauw,et al.  ClariNet: a noise analysis tool for deep submicron design , 2000, Proceedings 37th Design Automation Conference.

[15]  Masakazu Shoji,et al.  High-Speed Digital Circuits , 1996 .

[16]  Mark Mohammad Tehranipoor,et al.  Pattern generation and estimation for power supply noise analysis , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[17]  Sujit Dey,et al.  On-line testing of multi-source noise-induced errors on the interconnects and buses of system-on-chips , 2002, Proceedings. International Test Conference.

[18]  Anurag Mittal,et al.  Nano-CMOS Circuit and Physical Design , 2004 .

[19]  Robert H. Dennard,et al.  CMOS scaling for high performance and low power-the next ten years , 1995, Proc. IEEE.

[20]  D. Blaauw,et al.  Noise propagation and failure criteria for VLSI designs , 2002, ICCAD 2002.

[21]  Mehrdad Nourani,et al.  Test pattern generation for signal integrity faults on long interconnects , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[22]  Antonio Rubio,et al.  Noise generation and coupling mechanisms in deep-submicron ICs , 2002, IEEE Design & Test of Computers.

[23]  Masakazu Shoji,et al.  Theory of CMOS Digital Circuits and Circuit Failures , 1992 .

[24]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[25]  Daniel C. Edelstein,et al.  On-chip wiring design challenges for gigahertz operation , 2001, Proc. IEEE.

[26]  Mehrdad Nourani,et al.  Testing SoC interconnects for signal integrity using boundary scan , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[27]  Sharad Malik,et al.  Guest Editors' Introduction: Exploring Synergies for Design Verification , 2004, IEEE Des. Test Comput..

[28]  Víctor H. Champac,et al.  Testing Skew and Logic Faults in SoC Interconnects , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

[29]  Qiang Xu,et al.  Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs , 2007, 2007 IEEE International Test Conference.

[30]  Rajendran Panda,et al.  Crosstalk noise control in an SoC physical design flow , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[31]  L. Green.  Understanding the importance of signal integrity , 1999 .

[32]  Mehrdad Nourani,et al.  Detecting signal-overshoots for reliability analysis in high-speed system-on-chips , 2002, IEEE Trans. Reliab..