formed beneath theperipheral circuit. Fig.2 schematically showsthewellstructure andbias conditions. Negative bias is Floating BodyCell(FBC)isaone-transistor memorycellapplied toP-plate beneath thearray device toenhance signal on SOIsubstrate, whichaimshighdensity embeddedandretention time, andthesuitable backbias forNFETand memoryon SOC.Inorder toverify thismemorycellPFEToftheperipheral circuit canbeapplicable toeliminate technology, a 128MbSOIDRAM withFBC hasbeen thebacksurface leakage. designed andsuccessfully developed. Thememorycell Theoperation principle ofFD FBCisshowninFig.3 [3]. design, andtheexperimental results, suchasthesignal and Data"1"iswritten bycreating holes byimpact ionization theretention characteristics, arereviewed. Theresults ofthe andpushes upbodypotential tohigh level. Thecreated holes fabricated SOIDRAM andtheprospect asembeddedareaccumulated tothebacksurface bynegative plate bias. memoryarealso discussed. Ontheother hand, data"0"iswritten byextracting holes fromthebodyandpulls downthebodypotential tolowlevel.