Process graph analyzer: a front end tool for VHDL behavioral synthesis

A front end for an electronic CAD system is described. The system accepts a behavioral description of a digital system design written in VHDL (VHSIC Hardware Description Language), and produces the physical hardware, at the register-transfer level, needed for realizing the specified behavior. The synthesis system comprises three major subsystems: process graph analyzer, design representation, and the MIMOLA synthesis system. The process graph analyzer is an optimization and parallelization tool. It is shown how optimizing techniques used for compilers are adapted to perform a similar optimization function for hardware synthesis. Techniques are presented that extend the parallelization of sequential programs concept for doing control-state partitioning. The technique is novel because of the unique synthesis model that MIMOLA uses. It is shown how to integrate these concepts using a suitable intermediate behavioral representation called the process graph.<<ETX>>