High Level Synthesis by Systematic Derivation of Vision Automata from Emulation Results

A methodology for deriving image processing ASICs from the results of their real-time emulation on the Data-Flow Functional Computer is presented. The aim of the method is to reduce the time and effort required for synthesizing and validating ASICs after emulation. Indeed, the same architecture which emulated the application is the entry point of the derivation process. Thus, the “synthesis” is restricted to the optimization at the Register-Transfer level of the validated emulator architecture, as a consequence the validation of derived ASICs is easier. The derivation process is demonstrated on the direction extraction macro of a defect detector application.

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