A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using Gm-C-Based Noise-Shaped Quantizer and Digital Integrator

This paper presents a continuous-time (CT) delta-sigma modulator using a Gm-C based noise-shaped integrating quantizer (NSIQ) with a digital back-end integrator. By incorporating the digital back-end integrator, the tradeoff between resolution and speed for a conventional time-based NSIQ is alleviated. Using only three clock edges and a low-power Gm-C, effective 4-bit quantization with an additional first order noise-shaping is achieved. Also, the linearity requirement of the quantizer is relaxed by employing the digital back-end integrator. The proposed modulator was fabricated in a 0.13 $\mu \text {m}$ CMOS process with an active area of 0.08 $\text {mm}^{2}$ . It operates at 640 MHz and achieves a peak SNDR of 75.3 dB and a peak SFDR of 94.1 dB in a 10 MHz bandwidth while consuming 7.2 mW from a 1.2 V power supply.

[1]  C. Holuigue,et al.  A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB , 2006, IEEE Journal of Solid-State Circuits.

[2]  Shanthi Pavan,et al.  Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering , 2014, IEEE Journal of Solid-State Circuits.

[3]  Michael H. Perrott,et al.  A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer , 2008, VLSIC 2008.

[4]  William Yang,et al.  A Continuous-Time 0–3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.

[5]  Chun-Cheng Liu,et al.  A 0.022 mm$^{{2}}$ 98.5 dB SNDR Hybrid Audio $\Delta \Sigma$ Modulator With Digital ELD Compensation in 28 nm CMOS , 2015, IEEE Journal of Solid-State Circuits.

[6]  A. K. Gupta,et al.  A Two-Stage ADC Architecture With VCO-Based Second Stage , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Robert H. M. van Veldhoven,et al.  An Inverter-Based Hybrid ΔΣ Modulator , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[8]  W. Snelgrove,et al.  Excess loop delay in continuous-time delta-sigma modulators , 1999 .

[9]  T. S. Fiez,et al.  An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT $\Delta \Sigma$ Modulator Dissipating 13.7-mW , 2013, IEEE Journal of Solid-State Circuits.

[10]  Pavan Kumar Hanumolu,et al.  A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications , 2015, IEEE Journal of Solid-State Circuits.

[11]  F. Maloberti,et al.  A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order $\Sigma \Delta$ Modulator , 2012, IEEE Journal of Solid-State Circuits.

[12]  Un-Ku Moon,et al.  A Third-Order DT $\Delta\Sigma$ Modulator Using Noise-Shaped Bi-Directional Single-Slope Quantizer , 2011, IEEE Journal of Solid-State Circuits.

[13]  M.H. Perrott,et al.  A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$m CMOS , 2009, IEEE Journal of Solid-State Circuits.

[14]  David A. Johns,et al.  A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20MHz signal bandwidth , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[15]  Koji Obata,et al.  A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[16]  D.A. Johns,et al.  A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth , 2006, IEEE Journal of Solid-State Circuits.

[17]  Thomas Blon,et al.  A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB , 2006 .

[18]  N. Weste,et al.  A 500 MHz CMOS anti-alias filter using feed-forward op-amps with local common-mode feedback , 2003 .

[19]  Un-Ku Moon,et al.  A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step Integrating Quantizer , 2013, IEEE Journal of Solid-State Circuits.

[20]  Amr Elshazly,et al.  A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer , 2012, IEEE Journal of Solid-State Circuits.

[21]  Georges Gielen,et al.  A 14-bit intrinsic accuracy Q2 random walk CMOS DAC , 1999, IEEE J. Solid State Circuits.

[22]  John G. Kauffman,et al.  A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW , 2014, IEEE Journal of Solid-State Circuits.

[23]  Pavan Kumar Hanumolu,et al.  A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[24]  Ian Galton,et al.  A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB , 2013, IEEE Journal of Solid-State Circuits.

[25]  Hajime Shibata,et al.  A DC-to-1 GHz Tunable RF Delta Sigma ADC Achieving DR = 74 dB and BW = 150 MHz at f0 = 450 MHz Using 550 mW , 2012, IEEE J. Solid State Circuits.

[26]  M.Z. Straayer,et al.  A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer , 2008, IEEE Journal of Solid-State Circuits.

[27]  Randall L. Geiger,et al.  Formulation of INL and DNL yield estimation in current-steering D/A converters , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).