A single ended write double ended read decoupled 8-T SRAM cell with improved read stability and writability

In this paper a single ended write double ended read decoupled SRAM cell is proposed. Design metrics of the proposed cell are examined and compared with conventional 6-T. Proposed SRAM cell offer improvement during both read and write operation in terms of speed. It offers 2.95× shorter read delay. It exhibits 2.74× and 7.84× shorter write delay during write-1 and write-0 respectively. The proposed cell also shows improvement in read stability and writability. It offers 5.07× higher RSNM (read static noise margin). It shows 4.08% improvement in WSNM (write static noise margin) @ 300 mV compared to conventional 6-T.

[1]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[2]  Kaushik Roy,et al.  A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[3]  Andrew Evert Carlson Device and circuit techniques for reducing variation in nanoscale SRAM , 2008 .

[4]  K. Ishibashi,et al.  A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits , 2007, IEEE Journal of Solid-State Circuits.

[5]  David Blaauw,et al.  Analysis and mitigation of variability in subthreshold design , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[6]  C. Radens,et al.  A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing , 2008, IEEE Journal of Solid-State Circuits.

[7]  C.H. Kim,et al.  A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing , 2008, IEEE Journal of Solid-State Circuits.

[8]  Kaushik Roy,et al.  Ultra-low power digital subthreshold logic circuits , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[9]  A. Chandrakasan,et al.  A 180-mV subthreshold FFT processor using a minimum energy design methodology , 2005, IEEE Journal of Solid-State Circuits.

[10]  A.P. Chandrakasan,et al.  A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation , 2007, IEEE Journal of Solid-State Circuits.

[11]  E. Nowak,et al.  Low-power CMOS at Vdd = 4kT/q , 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).

[12]  Kaushik Roy,et al.  Ultra-low-power DLMS adaptive filter for hearing aid applications , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[13]  H. Fujiwara,et al.  Which is the best dual-port SRAM in 45-nm process technology? — 8T, 10T single end, and 10T differential — , 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.