On-Line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project

The progress in hardware technologies for implementing portable, low power and low cost electronic systems for consumer products has been major the last years. The complexity of embedded systems will further increase at a rate which is not met by the development of advanced CAD tools for managing the large design space. This will likely lead to increased design problems regarding system implementation, test and verification. In the next 15-20 years, it is likely that the consumer products are based on computing devices which are grouped together in networks including thousands or even millions of nodes. The /ETHER project deals with managing the complexity of such systems based on emerging technologies for future applications. This paper presents how the design complexity can be managed at the hardware level by integrating self-adaptive characteristics, and how the trade-off in performance and flexibility can be optimized to fulfill all application requirements while reducing the design complexity.

[1]  Mahmut T. Kandemir,et al.  A crosstalk aware interconnect with variable cycle transmission , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[2]  Giovanni De Micheli,et al.  An adaptive low-power transmission scheme for on-chip networks , 2002, 15th International Symposium on System Synthesis, 2002..

[3]  Chris R. Jesshope.  muTC - An Intermediate Language for Programming Chip Multiprocessors , 2006, Asia-Pacific Computer Systems Architecture Conference.

[4]  Jürgen Becker,et al.  Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics , 2005, ReCoSoC.

[5]  Jürgen Becker,et al.  An FPGA run-time system for dynamical on-demand reconfiguration , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[6]  Steven A. Guccione,et al.  XBI: a Java-based interface to FPGA hardware , 1998, Other Conferences.

[7]  David Blaauw,et al.  ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon , 2006, IEEE Design & Test of Computers.

[8]  Jürgen Becker,et al.  Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems , 2003, VLSI-SoC.

[9]  Mary Jane Irwin,et al.  Adapative Error Protection for Energy Efficiency , 2003, ICCAD 2003.

[10]  Taewhan Kim,et al.  Thermal sensor allocation and placement for reconfigurable systems , 2009, TODE.

[11]  Peter M. Athanas,et al.  An alternate wire database for Xilinx FPGAs , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[12]  M. J. Irwin,et al.  Adaptive error protection for energy efficiency , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[13]  J. Krikke.  Sunrise for energy harvesting products , 2005, IEEE Pervasive Computing.

[14]  J. Krikke.  T-Engine: Japan's ubiquitous computing architecture is ready for prime time , 2005, IEEE Pervasive Computing.

[15]  Jürgen Becker,et al.  On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives , 2006, SBCCI '06.