论文信息 - Influence of an accumulation back-gate voltage on the low-frequency noise spectra of 0.13 /spl mu/m fully-depleted SOI MOSFETs fabricated on ELTRAN and UNIBOND wafers

Influence of an accumulation back-gate voltage on the low-frequency noise spectra of 0.13 /spl mu/m fully-depleted SOI MOSFETs fabricated on ELTRAN and UNIBOND wafers

The behaviour of so-called back-gate induced Lorentzians has been investigated in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs, fabricated in a 0.13 /spl mu/m CMOS technology, on ELTRAN and UNIBOND wafers. While this excess low-frequency (LF) noise source is fairly easily observed in ELTRAN (E) p-and UNIBOND (U) nMOSFETs, when the back-gate voltage (V/sub GB/) is in accumulation, this is not true for their n-(E) and p-channel (U) counterparts. It is be demonstrated that the origin of this novel noise source resembles the one of the electron valence band (EVB) tunnelling related Lorentzians, although it occurs at front-gate voltages below the EVB tunnelling threshold. It is shown that in this case, the RC-filtered Nyquist noise of the source and drain junctions at the back interface is the main cause of the excess Lorentzians.

E. Simoen | C. Claeys | A. Smolanka | N. Litkyanchikova | N. Garbar

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