Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop
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Sayed Masoud Sayedi | Hossein Saidi | Hossein Karimiyan Alidash | H. K. Alidash | H. Saidi | S. Sayedi
[1] Kaushik Roy,et al. Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories , 2000, ISLPED '00.
[2] Mark Vesterbacka. A robust differential scan flip-flop , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).
[3] James Tschanz,et al. Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors , 2001, ISLPED '01.
[4] Mohamed A. Elgamel,et al. Design methodologies for high-performance noise-tolerant XOR-XNOR circuits , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.
[5] Eby G. Friedman,et al. Multi-Voltage CMOS Circuit Design: Kursun/Multi-Voltage CMOS Circuit Design , 2006 .
[6] A.P. Chandrakasan,et al. A leakage reduction methodology for distributed MTCMOS , 2004, IEEE Journal of Solid-State Circuits.
[7] Satoshi Shigematsu,et al. A 1-V high-speed MTCMOS circuit scheme for power-down application circuits , 1997, IEEE J. Solid State Circuits.
[8] Eby G. Friedman,et al. Multi-voltage CMOS Circuit Design , 2006 .
[9] Borivoje Nikolic,et al. Level conversion for dual-supply systems , 2004 .
[10] Kaushik Roy,et al. DRG-cache: a data retention gated-ground cache for low power , 2002, DAC '02.
[11] A. Chandrakasan,et al. MTCMOS sequential circuits , 2001, Proceedings of the 27th European Solid-State Circuits Conference.
[12] Vojin G. Oklobdzija,et al. Dual-edge triggered storage elements and clocking strategy for low-power systems , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[13] Saibal Mukhopadhyay,et al. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.
[14] Vojin G. Oklobdzija. Clocking and clocked storage elements in a multi-gigahertz environment , 2003, IBM J. Res. Dev..
[15] Andrew B. Kahng,et al. Impact of gate-length biasing on threshold-voltage selection , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).
[16] Vladimir Stojanovic,et al. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems , 1999, IEEE J. Solid State Circuits.
[17] Magdy A. Bayoumi,et al. Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.