Evaluation of an HLS-based heterogeneous redundant design approach for functional safety systems on FPGAs

Field programmable gate arrays (FPGAs) are now used in a wide range of application fields including aerospace, medical, and industrial infrastructure systems, where not only soft errors but also common cause faults must be treated in systems design. Although the heterogeneous redundant design is preferable in such application fields, it tends to be a large burden on system designers. Even with high-level synthesis (HLS) technologies, which have enabled productive design processes without register transfer level (RTL) descriptions, an efficient design approach for redundant design is not always clear. In this paper, we proposed a productive heterogeneous redundant design method, focusing on diversity in FPGA resources. Then, we implemented homogeneous and heterogeneous redundant designs for PID control, using RTL and HLS, and evaluated their error detection capability and reliability. The simulation results showed that heterogeneous redundant designs by the proposed method have a high error detection rate in both RTL and HLS implementations in an application-level circuit.