Generic partial dynamic reconfiguration controller for fault tolerant designs based on FPGA

In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The basic architecture and usage of the controller in the FPGA-based fault tolerant structure are described. The implementation of controller as fault tolerant component is described as well. The basic features and synthesis results of controller for Xilinx FPGA and comparison with MicroBlaze solution are presented.

[1]  Greg Miller,et al.  Teaching Fault Tolerant FPGA Design for Aerospace Applications , 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).

[2]  Marco D. Santambrogio,et al.  TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[3]  Alan D. George,et al.  Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[4]  Edward J. McCluskey,et al.  On-line testing and recovery in TMR systems for real-time applications , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[5]  Mikel Azkarate-askasua,et al.  A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[6]  Michael J. Wirthlin,et al.  FPGA partial reconfiguration via configuration scrubbing , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[7]  Dionisios N. Pnevmatikatos,et al.  A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[8]  Tapan J. Chakraborty,et al.  A TMR Scheme for SEU Mitigation in Scan Flip-Flops , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[9]  Martin Straka,et al.  Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration , 2010, DSD 2010.

[10]  Luigi Carro,et al.  Designing fault-tolerant techniques for SRAM-based FPGAs , 2004, IEEE Design & Test of Computers.

[11]  Zdenek Kotásek,et al.  Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs , 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

[12]  J. Torresen,et al.  Partial Reconfiguration Applied in an On-line Evolvable Pattern Recognition System , 2008, 2008 NORCHIP.

[13]  Luca Sterpone,et al.  On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications , 2008, 2008 Design, Automation and Test in Europe.