A novel hardware accelerator architecture for MPEG-2/4 AAC encoder
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A VLSI architecture for the MPEG-2/4 AAC encoding accelerator is proposed This hardware IP is an AMBA AHB peripheral component that can easily integrate with any other RISC based SoC platform. Preserving the flexibility of library development and achieving an area cost-efficient acceleration, the quantisation rate-loop module is targeted to be the processing function. In the design, an easy Huffman codebook search method is also developed for the viability of hardware realization. The final work has been verified in an FPGA and synthesized to a 0.18 mum standard cell library. It can speed up an audio recording application by 1.5-times and achieve a real-time encoding for stereo 44.1 kHz PCM data with additional 160 MHz ARM core
[1] Takao Onoye,et al. A Hardware Implementation of Ogg Vorbis Audio Decoder with Embedded Processor , 2002 .
[3] S. Gadd,et al. A Hardware Accelerated MP3 Decoder with Bluetooth Streaming capabilities , 2001 .