An Analysis of Processor-Memory Interconnection Networks

An interference analysis of the interconnection networks (IN's) for tightly coupled multiprocessors is presented in this correspondence. The interconnections considered are crossbars and delta networks. Two situations are examined: when a memory module is equally likely to be addressed by a processor and when a processor has a favorite memory. It is shown that for a higher rate of favorite requests, the delta networks perform close to a crossbar.

[1]  Dileep Bhandarkar,et al.  Analysis of Memory Interference in Multiprocessors , 1975, IEEE Transactions on Computers.

[2]  Gordon Bell,et al.  C.mmp: a multi-mini-processor , 1972, AFIPS '72 (Fall, part II).

[3]  Daniel M. Dias,et al.  Analysis and Simulation of Buffered Delta Networks , 1981, IEEE Transactions on Computers.

[4]  Harold S. Stone,et al.  Parallel Processing with the Perfect Shuffle , 1971, IEEE Transactions on Computers.

[5]  Duncan H. Lawrie,et al.  Access and Alignment of Data in an Array Processor , 1975, IEEE Transactions on Computers.

[6]  Tse-yun Feng,et al.  A Survey of Interconnection Networks , 1981, Computer.

[7]  Suchai Thanawastien,et al.  Interference Analysis of Shuffle/Exchange Networks , 1981, IEEE Transactions on Computers.

[8]  Trevor Mudge,et al.  Probabilistic analysis of a crossbar switch , 1982, ISCA 1982.

[9]  Dharma P. Agrawal,et al.  Design and Performance of Generalized Interconnection Networks , 1983, IEEE Transactions on Computers.

[10]  Janak H. Patel Performance of Processor-Memory Interconnections for Multiprocessors , 1981, IEEE Transactions on Computers.