A 5-bit 1.35-GSPS DAC for UWB transceivers

This paper presents a low-power 5-bit 1.35-GSPS current-steering digital-to-analog converter (DAC) for ultra-wideband (UWB) transceivers. A “3 (thermometer) + 2 (binary)” segmented structure is used for reaching a compromise between the circuit complexity and differential nonlinearity (DNL) error. To save the power consumption while maintaining the same output voltage swing, a bipolar current source cell is employed. Besides, a de-glitch latch is presented to reduce the clock feedthrough from the pass transistors. This DAC was implemented in a standard 0.18-µm 1P6M CMOS technology. The measured integral nonlinearity (INL) and the differential nonlinearity (DNL) are less than 0.04 LSB and 0.05 LSB, respectively. The spurious-free dynamic range (SFDR) is above 30 dB over the complete Nyquist band at a sampling rate of 1.35 GHz. The power consumption of this DAC is 9.7 mW. The active area of the circuit occupies 0.19 mm2.

[1]  Michel Steyaert,et al.  A 12-bit intrinsic accuracy high-speed CMOS DAC , 1998, IEEE J. Solid State Circuits.

[2]  M. P. Tiilikainen.  A 14-bit 1.8-V 20-mW 1-mm/sup 2/ CMOS DAC , 2001 .

[3]  K. O'Sullivan,et al.  A 12-bit 320-MSample/s current-steering CMOS D/A converter in 0.44 mm/sup 2/ , 2004, IEEE Journal of Solid-State Circuits.

[4]  D.A. Johns,et al.  A CMOS 10-gb/s power-efficient 4-PAM transmitter , 2004, IEEE Journal of Solid-State Circuits.

[5]  Day-Uei Li,et al.  1 V 1.25 GS/s 8 mW D/A Converters for MB-OFDM UWB Transceivers , 2007, 2007 IEEE International Conference on Ultra-Wideband.

[6]  W. Sansen,et al.  A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter , 2001, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[7]  Georges Gielen,et al.  A 14-bit intrinsic accuracy Q2 random walk CMOS DAC , 1999, IEEE J. Solid State Circuits.

[8]  M.S.J. Steyaert,et al.  A 10-bit 250-MS/s binary-weighted current-steering DAC , 2004, IEEE Journal of Solid-State Circuits.

[9]  Hae-Seung Lee,et al.  Output impedance requirements for DACs , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[10]  K. Bult,et al.  A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2 , 1998, IEEE J. Solid State Circuits.