Device/Circuit co-design guide for passive memristor array with non-linear current-voltage behavior.

In this paper, the non-linearity in memristor's current-voltage relationship that can affect half-selected cells is analyzed. From the simulation, for the V(DD)/2 scheme, if the non-linear coefficient is larger than 8, unwanted resistance loss during the write time can be suppressed less than 10%. Comparing the V(DD)/2 and V(DD)/3 scheme, the V(DD)/2 scheme can reduce the current consumption by 2 orders of magnitude with little larger resistance change in half-selected cells than the V(DD)/3.