A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler

A high-speed CMOS TSPC divide-by-16/17 dual modulus prescaler is proposed. The speed of the prescaler is improved in two aspects. First, by adopting a new pseudo divide-by-2/3 prescaler, the minimum working period is effectively reduced by half a NOR gate's delay. Second, by changing the connection of TSPC D-Flip-Flops, the minimum working period is further reduced by half an inverter's delay. Simulation results show that the maximum operating frequency of the proposed circuit is improved by ~40% compared with conventional circuit. Fabricated in 0.18-μm CMOS process, the proposed circuit is capable of operating up to 5.8 GHz. The power consumption is 2.6 mW at the maximum operating frequency under 1.6 V supply voltage.

[1]  Byunghoo Jung,et al.  High-Speed Low-Power True Single-Phase Clock Dual-Modulus Prescalers , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Xiaopeng Yu,et al.  6.1 GHz 4.6 mW CMOS divide-by-55/56 prescaler , 2008 .

[3]  Byungsoo Chang,et al.  A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops , 1996 .

[4]  Choongyeun Cho,et al.  A 94GHz Locking Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[5]  T. Kuroda,et al.  A 20-GHz Injection-Locked LC Divider with a 25-% Locking Range , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[6]  Kiat Seng Yeo,et al.  Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[8]  Hyunchol Shin.  A 1-V TSPC Dual Modulus Prescaler with Speed Scalability Using Forward Body Biasing in 0.18 µm CMOS , 2012, IEICE Trans. Electron..

[9]  Seungsoo Kim,et al.  An E-TSPC Divide-by-2 Circuit With Forward Body Biasing in 0.25 $\mu$ m CMOS , 2009, IEEE Microwave and Wireless Components Letters.

[10]  Kiat Seng Yeo,et al.  Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler , 2006, IEEE Transactions on Microwave Theory and Techniques.

[11]  M. Sokolich,et al.  State of the art low power (42 mW per flip-flop) 150 GHz+ CML static divider implemented in scaled 0.2 m emitter-width InP DHBTs , 2006, 2006 International Conference on Indium Phosphide and Related Materials Conference Proceedings.

[12]  Kiat Seng Yeo,et al.  A Low-Power Single-Phase Clock Multiband Flexible Divider , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Shen-Iuan Liu,et al.  New dynamic flip-flops for high-speed dual-modulus prescaler , 1998, IEEE J. Solid State Circuits.

[14]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .