Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits

This paper proposes body-bias generator for leakage power reduction of digital logic circuits which operates at low supply voltage of 0.5V. The proposed circuit adopts double charge pumping scheme to enhance the pumping gain. The proposed circuit is fabricated using 0.13 μm CMOS process and measurement result demonstrates stable operation with body-bias voltage of -0.95V. We apply the proposed circuit to 64-bit carry look-ahead adder to demonstrate its performance. We report that the leakage power of 64-bit carry look-ahead adder can dramatically be reduced by adopting proposed substratebias generator. The estimated leakage power reduction is 90% (T=75°C).

[1]  Kyeong-Sik Min,et al.  A fast pump-down V/sub BB/ generator for sub-1.5-V DRAMs , 2001 .

[2]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[3]  Anantha Chandrakasan,et al.  Optimal supply and threshold scaling for subthreshold CMOS circuits , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[4]  Michel Declercq,et al.  A high-efficiency CMOS voltage doubler , 1998, IEEE J. Solid State Circuits.

[5]  Tadayoshi Enomoto,et al.  A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications , 2003, IEEE J. Solid State Circuits.

[6]  Yoshikazu Morooka,et al.  An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs , 1994 .

[7]  J. F. Dickson,et al.  On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique , 1976 .

[8]  T. Fujita,et al.  A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[9]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[10]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .

[11]  Y. J. Park,et al.  A new charge pump without degradation in threshold voltage due to body effect [memory applications] , 2000, IEEE Journal of Solid-State Circuits.