A Design of Input-Decimation Technique for Recursive DFT/IDFT Algorithm

In this paper, an input-decimation technique for the recursive discrete Fourier transform (RDFT)/inverse DFT (RIDFT) algorithm is proposed for the high-speed broadband communication systems. It is worth noting that the input-decimation approach is presented to decrease the number of input sequences for the recursive filter so that the computation cycle of RDFT/RIDFT can be shortened to meet the computing time requirement (<inline-formula> <tex-math notation="LaTeX">$3.6~{\mu }s$ </tex-math></inline-formula>) for the high-speed broadband communication systems. Therefore, the input-decimation RDFT/RIDFT algorithm is able to carry out at least 55.5% reduction of the total computation cycles compared with the considered algorithms. Furthermore, holding the advantages of input-decimation technique, the computational complexities of the real-multiplication and -addition are reduced to 41.3% and 22.2%, respectively. The area and the power consumption can be minimized by employing the cost-efficient constant multiplier with the refined signed-digit expression of twiddle factors. Finally, the physical implementation results show that the core area is <inline-formula> <tex-math notation="LaTeX">$0.37\times 0.37$ </tex-math></inline-formula> mm<sup>2</sup> with <inline-formula> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS process. The power consumption is 5.16 mW with the supply voltage of 1.8 V and the operating clock of 40 MHz. The proposed design can achieve 258 million of computational efficiency per unit area (CEUA) and really outperform the previous works.

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