论文信息 - Topology design for global link optimization in application specific network-on-chips

Topology design for global link optimization in application specific network-on-chips

A new algorithm for application-specific network-on-chip design and optimization is presented. The algorithm uses packet-scheduling and traffic modelling concepts to estimate the degree of interaction of several communication channels (congestion) on a given design. It is implemented as part of a network design software package that includes other optimization criteria, like power consumption and reliability.

Jari Nurmi | David A. Sigüenza-Tortosa

[1] Jari Nurmi,et al. An IP-Based On-Chip Packet-Switched Network , 2003, Networks on Chip.

[2] Benjamin Melamed,et al. Hybrid discrete-continuous fluid-flow simulation , 2001, SPIE ITCom.

[3] J. Cong,et al. Interconnect design for deep submicron ICs , 1997, ICCAD 1997.

[4] Baruch Awerbuch,et al. Universal-stability results and performance bounds for greedy contention-resolution protocols , 2001, JACM.

[5] Tapani Ahonen,et al. Topology optimization for application-specific networks-on-chip , 2004, SLIP '04.

[6] William J. Dally,et al. Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[7] Wolfgang Fichtner,et al. Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).