Temporal Antecedent Failure: Refining Vacuity

We re-examine vacuity in temporal logic model checking. We note two disturbing phenomena in recent results in this area. The first indicates that not all vacuities detected in practical applications are considered a problem by the system verifier. The second shows that vacuity detection for certain logics can be very complex and time consuming. This brings vacuity detection into an undesirable situation where the user of the model checking tool may find herself waiting a long time for results that are of no interest for her. In this paper we define Temporal Antecedent Failure, an extension of antecedent failure to temporal logic, which refines the notion of vacuity. According to our experience, this type of vacuity always indicates a problem in the model, environment or formula. On top, detection of this vacuity is extremely easy to achieve. We base our definition and algorithm on regular expressions, that have become the major temporal logic specification in practical applications.

[1]  Dana Fisman,et al.  The Safety Simple Subset , 2005, Haifa Verification Conference.

[2]  Edmund M. Clarke,et al.  Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic , 1981, Logic of Programs.

[3]  Marsha Chechik,et al.  Finding Environment Guarantees , 2007, FASE.

[4]  Marsha Chechik,et al.  Extending Extended Vacuity , 2004, FMCAD.

[5]  Zeljko Zilic,et al.  Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties , 2006, HLDVT.

[6]  Ilan Beer,et al.  Efficient Detection of Vacuity in Temporal Model Checking , 2001, Formal Methods Syst. Des..

[7]  C. Eisner,et al.  Efficient Detection of Vacuity in ACTL Formulaas , 1997, CAV.

[8]  Jerzy Tiuryn,et al.  Logics of Programs , 1991, Handbook of Theoretical Computer Science, Volume B: Formal Models and Sematics.

[9]  J. Havlicek,et al.  Automata Construction for PSL , 2005 .

[10]  Zeljko Zilic,et al.  Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties , 2006, 2006 IEEE International High Level Design Validation and Test Workshop.

[11]  Joseph Sifakis,et al.  Specification and verification of concurrent systems in CESAR , 1982, Symposium on Programming.

[12]  Orna Grumberg,et al.  Automatic Refinement and Vacuity Detection for Symbolic Trajectory Evaluation , 2006, CAV.

[13]  Kedar S. Namjoshi An Efficiently Checkable, Proof-Based Formulation of Vacuity in Model Checking , 2004, CAV.

[14]  D. Fisman,et al.  A Practical Introduction to PSL (Series on Integrated Circuits and Systems) , 2006 .

[15]  George J. Milne,et al.  Correct Hardware Design and Verification Methods , 2003, Lecture Notes in Computer Science.

[16]  Helmut Veith,et al.  Parameterized Vacuity , 2004, FMCAD.

[17]  Kenneth L. McMillan,et al.  Symbolic model checking , 1992 .

[18]  Orna Kupferman,et al.  Vacuity Detection in Temporal Model Checking , 1999, CHARME.

[19]  Dana Fisman,et al.  Automata Construction for Regular Expressions in Model Checking , 2004 .

[20]  Orna Grumberg,et al.  Enhanced Vacuity Detection in Linear Temporal Logic , 2003, CAV.

[21]  Stephan Merz,et al.  Model Checking , 2000 .

[22]  C. R. Ramakrishnan,et al.  Vacuity Checking in the Modal Mu-Calculus , 2002, AMAST.

[23]  Dana Fisman,et al.  Embedding finite automata within regular expressions , 2008, Theor. Comput. Sci..

[24]  Ilan Beer,et al.  On-the-Fly Model Checking of RCTL Formulas , 1998, CAV.

[25]  Orna Grumberg,et al.  Regular Vacuity , 2005, CHARME.

[26]  Gérard Berry,et al.  From Regular Expressions to Deterministic Automata , 1986, Theor. Comput. Sci..

[27]  Marsha Chechik,et al.  How Vacuous Is Vacuous? , 2004, TACAS.

[28]  Randal E. Bryant,et al.  Formally Verifying a Microprocessor Using a Simulation Methodology , 1994, 31st Design Automation Conference.

[29]  Rajeev Alur,et al.  A Temporal Logic of Nested Calls and Returns , 2004, TACAS.

[30]  Fabio Somenzi,et al.  Vacuum Cleaning CTL Formulae , 2002, CAV.

[31]  Dana Fisman,et al.  A Practical Introduction to PSL , 2006, Series on Integrated Circuits and Systems.