ADVANCED TIMING AND SYNCHRONIZATION METHODOLOGIES FOR DIGITAL VLSI INTEGRATED CIRCUITS

This dissertation addresses timing and synchronization methodologies that are critical to the design, analysis and optimization of high-performance, integrated digital VLSI systems. As process sizes shrink and design complexities increase, achieving timing closure for digital VLSI circuits becomes a significant bottleneck in the integrated circuit design flow. Circuit designers are motivated to investigate and employ alternative methods to satisfy the timing and physical design performance targets. Such novel methods for the timing and synchronization of complex circuitry are developed in this dissertation and analyzed for performance and applicability.Mainstream integrated circuit design flow is normally tuned for zero clock skew, edge-triggered circuit design. Non-zero clock skew or multi-phase clock synchronization is seldom used because the lack of design automation tools increases the length and cost of the design cycle. For similar reasons, level-sensitive registers have not become an industry standard despite their superior size, speed and power consumption characteristics compared to conventional edge-triggered flip-flops.In this dissertation, novel design and analysis techniques that fully automate the design and analysis of non-zero clock skew circuits are presented. Clock skew scheduling of both edge-triggered and level-sensitive circuits are investigated in order to exploit maximum circuit performances. The effects of multi-phase clocking on non-zero clock skew, level-sensitive circuits are investigated leading to advanced synchronization methodologies. Improvements in the scalability of the computational timing analysis process with clock skew scheduling are explored through partitioning and parallelization.The integration of the proposed design and analysis methods to the physical design flow of integrated circuits synchronized with a next-generation clocking technology-resonant rotary clocking technology-is also presented. Based on the design and analysis methods presented in this dissertation, a computer-aided design tool for the design of rotary clock synchronized integrated circuits is developed.

[1]  Douglas A. Pucknell,et al.  Basic VLSI Design , 1987 .

[2]  B. Korte,et al.  Clock scheduling and clocktree construction for high performance ASICs , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[3]  Nasser A. Kurd,et al.  A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor , 2001, IEEE J. Solid State Circuits.

[4]  Baris Taskin,et al.  Delay insertion method in clock skew scheduling , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Trevor N. Mudge,et al.  Critical paths in circuits with level-sensitive latches , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Bruce Hendrickson,et al.  A Multi-Level Algorithm For Partitioning Graphs , 1995, Proceedings of the IEEE/ACM SC95 Conference.

[7]  Baris Taskin,et al.  Linear timing analysis of SOC synchronous circuits with level-sensitive latches , 2002, 15th Annual IEEE International ASIC/SOC Conference.

[8]  Sachin S. Sapatnekar,et al.  A practical algorithm for retiming level-clocked circuits , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

[9]  James D. Warnock.  Circuit design issues for the POWER4 chip , 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

[10]  Dhanistha Panyasak,et al.  Circuits , 1995, Annals of the New York Academy of Sciences.

[11]  S. Lipa,et al.  Rotary traveling-wave oscillator arrays: a new clock technology , 2001 .

[12]  Vernon L. Chi.  Salphasic Distribution of Clock Signals for Synchronous Systems , 1994, IEEE Trans. Computers.

[13]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[14]  Eby G. Friedman.  Clock distribution networks in VLSI circuits and systems , 1995 .

[15]  Mark A. Clements,et al.  Clock distribution using cooperative ring oscillators , 1997, Proceedings Seventeenth Conference on Advanced Research in VLSI.

[16]  A. Sedra.  Microelectronic circuits , 1982 .

[17]  David H. C. Du,et al.  Enhancing circuit performance under a multiple-phase clocking scheme , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[18]  J. S. Denker,et al.  A review of adiabatic computing , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[19]  Kenneth C. Smith,et al.  Microelectronic circuits, 2nd ed. , 1987 .

[20]  Charles E. Leiserson,et al.  Retiming synchronous circuitry , 1988, Algorithmica.

[21]  Baris Taskin,et al.  Performance improvement of edge-triggered sequential circuits , 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

[22]  Jeong-Taek Kong,et al.  CAD for nanometer silicon design challenges and success , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  Baris Taskin,et al.  Linearization of The Timing Analysis and Optimization of Level-Sensitive Circuits , 2003 .

[24]  K. Nose,et al.  Parallel clocking: a multi-phase clock-network for 10GHz SoC , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[25]  Robert K. Brayton,et al.  Graph algorithms for clock schedule optimization , 1992, ICCAD.

[26]  Eby G. Friedman,et al.  A quadratic programming approach to clock skew scheduling for reduced sensitivity to process parameter variations , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[27]  Kenneth L. Shepard,et al.  Design of resonant global clock distributions , 2003, Proceedings 21st International Conference on Computer Design.

[28]  Charles M. Fiduccia,et al.  A linear-time heuristic for improving network partitions , 1988, 25 years of DAC.

[29]  B. Hendrickson.  The Chaco User � s Guide Version , 2005 .

[30]  Ching-Te Chuang,et al.  A 400 MHz S/390 microprocessor , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[31]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[32]  T. Xanthopoulos,et al.  The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[33]  Suhwan Kim,et al.  Single-phase source-coupled adiabatic logic , 1999, ISLPED '99.

[34]  K. O.,et al.  A technique for incorporation of a heatsink for a system utilizing integrated circuits with wireless connections to an off-chip antenna , 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).

[35]  John P. Uyemura.  Introduction to VLSI Circuits and Systems , 2001 .

[36]  Baris Taskin,et al.  Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[37]  Alex Pothen,et al.  PARTITIONING SPARSE MATRICES WITH EIGENVECTORS OF GRAPHS* , 1990 .

[38]  Carl Ebeling,et al.  Optimal retiming of level-clocked circuits using symmetric clock schedules , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[39]  Madhavan Swaminathan,et al.  On the micro-architectural impact of clock distribution using multiple PLLs , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[40]  J. Wood,et al.  Multi-gigahertz low-power low-skew rotary clock scheme , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[41]  Baris Taskin,et al.  Timing Optimization Through Clock Skew Scheduling , 2000 .

[42]  Donhee Ham,et al.  Standing wave oscillators utilizing wave-adaptive tapered transmission lines , 2004, IEEE Journal of Solid-State Circuits.

[43]  K.A. Jenkins,et al.  A clock distribution network for microprocessors , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[44]  Chih-Ming Hung,et al.  Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters , 2002, IEEE J. Solid State Circuits.

[45]  S. Griffis.  EDITOR , 1997, Journal of Navigation.

[46]  Baris Taskin,et al.  Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew , 2002, TAU '02.

[47]  T. G. Szymanski,et al.  Verifying clock schedules , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[48]  Samuel D. Naffziger,et al.  The implementation of the Itanium 2 microprocessor , 2002, IEEE J. Solid State Circuits.

[49]  Robert K. Brayton,et al.  Minimum padding to satisfy short path constraints , 1993, ICCAD '93.

[50]  John A. Ludwig,et al.  Analyzing cycle stealing on synchronous circuits with level-sensitive latches , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[51]  Michel Dagenais,et al.  On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[52]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[53]  Bjarne Stroustrup,et al.  The C++ Programming Language: Special Edition , 2000 .

[54]  Jens Vygen,et al.  Cycle time and slack optimization for VLSI-chips , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[55]  B. Flachs,et al.  A 1 GHz single-issue 64 b PowerPC processor , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[56]  Trevor N. Mudge,et al.  CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[57]  Chak-Kuen Wong,et al.  A timing analysis algorithm for circuits with level-sensitive latches , 1994, ICCAD '94.

[58]  T.Y. Nguyen,et al.  Resonant clocking using distributed parasitic capacitance , 2004, IEEE Journal of Solid-State Circuits.

[59]  K.L. Shepard,et al.  A 4.6GHz resonant global clock distribution network , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[60]  Carl Ebeling,et al.  On the performance of level-clocked circuits , 1995, Proceedings Sixteenth Conference on Advanced Research in VLSI.

[61]  Kunle Olukotun,et al.  Analysis and design of latch-controlled synchronous digital circuits , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[62]  Hai Zhou,et al.  Clock schedule verification with crosstalk , 2002, TAU '02.

[63]  Baris Taskin,et al.  Advanced timing of level-sensitive sequential circuits , 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

[64]  Karem A. Sakallah,et al.  Optimization of critical paths in circuits with level-sensitive latches , 1994, ICCAD.

[65]  Andreas Kuehlmann,et al.  Multi-Domain Clock Skew Scheduling , 2003, ICCAD.

[66]  William H. Ford,et al.  Data Structures With C , 1996 .

[67]  C. Patrick Yue,et al.  Design of a 10GHz clock distribution network using coupled standing-wave oscillators , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[68]  Roy D. Williams,et al.  Performance of dynamic load balancing algorithms for unstructured mesh calculations , 1991, Concurr. Pract. Exp..

[69]  Thomas G. Szymanski,et al.  Computing optimal clock schedules , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[70]  G. Amdhal,et al.  Validity of the single processor approach to achieving large scale computing capabilities , 1967, AFIPS '67 (Spring).

[71]  Narendra V. Shenoy,et al.  Verifying clock schedules , 1992, ICCAD 1992.

[72]  John P. Fishburn,et al.  Clock Skew Optimization , 1990, IEEE Trans. Computers.

[73]  Narendra V. Shenoy,et al.  Efficient Implementation Of Retiming , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[74]  Marios C. Papaefthymiou,et al.  Edge-triggering vs. two-phase level-clocking , 1993 .

[75]  Guan-Chyun Hsieh,et al.  Phase-locked loop techniques. A survey , 1996, IEEE Trans. Ind. Electron..

[76]  M.A. Horowitz,et al.  Skew-tolerant domino circuits , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[77]  Shin Min Kang,et al.  CMOS Digital Integrated Cir-cuits: Analysis and Design , 2002 .

[78]  Eric R. Zieyel.  Operations research : applications and algorithms , 1988 .

[79]  Kia Bazargan,et al.  Multi-objective circuit partitioning for cutsize and path-based delay minimization , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[80]  Chih-Ming Hung,et al.  Wireless interconnects for clock distribution , 2002, TAU '02.

[81]  Shu-Cherng Fang,et al.  Linear Optimization and Extensions: Theory and Algorithms , 1993 .

[82]  Frank O'Mahony,et al.  A 10-GHz global clock distribution using coupled standing-wave oscillators , 2003 .

[83]  S.,et al.  An Efficient Heuristic Procedure for Partitioning Graphs , 2022 .