Systematic Extraction of Critical Areas From IC Layouts

We present a new method to determine the sensitivity of layouts to spot defects. The models for fatal faults considered are unintended bridges and unintended cuts related to patterns in one layer. Our method is a deterministic geometrical construction of so-called “critical areas”. The classical prototype of this construction consists of three steps (in the case of bridges): (1)Extend all patterns by half of the defect size; (2)Compute all the mutual intersections of the extended patterns; (3)Compute the area of the union of all intersections. Applying the scanline principle and assuming N line segments of the original mask patterns leads to an algorithm with asymptotic complexity N 2 logN 2, a bound which is sharp in particular for large defect sizes. Our approach, based on the new concept of “susceptible sites” reduces this complexity to NlogN. Moreover only two scans are necessary to extract all “susceptible sites” which then are used to compute the “critical areas” for a whole set of points in a domain of defect sizes. Under a UNIX-C environment an implementation has been created which actually exhibits the theoretically predicted gain in speed. Complex layouts can be analysed under interactive operating conditions on standard workstations (in our case of the type Apollo 3000).