FIRGEN: a computer-aided design system for high performance FIR filter integrated circuits

The authors describe automatic architecture and floorplan generation techniques for integrated circuit fixed-coefficient FIR (finite impulse response) filters that can achieve high sample rates with compact layouts. These techniques have been implemented in a filter design system called FIRGEN that can automate the entire design from filter specifications to final chip layout. It can be retargeted to new cell libraries and place and route tools. Result on four chips designed with FIRGEN are presented. These achieve sample rates ranging from 25 MHz to 112 MHz. >

[1]  Charles E. Leiserson,et al.  Optimizing synchronous systems , 1981, 22nd Annual Symposium on Foundations of Computer Science (sfcs 1981).

[2]  Jan M. Rabaey,et al.  An Integrated Automated Layout Generation System for DSP Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  A. Delaruelle,et al.  A digital audio filter using semi-automated design , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  Gilles Privat,et al.  Design of Digital Filters for Video Circuits , 1986 .

[5]  Robert W. Brodersen,et al.  Computer Generation of Digital Filter Banks , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  G. Goossens,et al.  Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system , 1986 .

[7]  M. Hatamian,et al.  A 70-MHz 8-bit/spl times/8-bit parallel pipelined multiplier in 2.5-/spl mu/m CMOS , 1986 .

[8]  F.F. Yassa,et al.  A silicon compiler for digital signal processing: Methodology, implementation, and applications , 1987, Proceedings of the IEEE.

[9]  P.R. Cappello,et al.  Computer-aided design of VLSI FIR filters , 1987, Proceedings of the IEEE.

[10]  M. Hatamian,et al.  Parallel bit-level pipelined VLSI designs for high-speed signal processing , 1987, Proceedings of the IEEE.

[11]  H. Samueli The design of multiplierless FIR filters for compensating D/A converter frequency response distortion , 1988 .

[12]  Barbara Joan Roeder,et al.  Decoding issues in the ACTV system , 1988 .

[13]  P. A. Ruetz,et al.  The architectures and design of a 20-MHz real-time DSP chip set , 1989 .

[14]  C. K. Birdsall Electronics Research Laboratory, Plasma Theory and Simulation Group annual progress report, January 1, 1989--December 31, 1989 , 1989 .

[15]  H. Samueli,et al.  A CMOS bit-level pipelined implementation of an FIR x/sin(x) predistortion digital filter , 1989, IEEE International Symposium on Circuits and Systems,.

[16]  R. Hartley,et al.  A high speed FIR filter designed by compiler , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[17]  C. Chien,et al.  FIRGEN: a CAD system for automatic layout generation of high-performance FIR filter , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[18]  Henry Samueli,et al.  A VLSI Architecture for a High-Speed All-Digital Quadrature Modulator and Demodulator for Digital Radio Applications , 1990, IEEE J. Sel. Areas Commun..

[19]  P. T. Yang,et al.  A functional silicon compiler for high speed FIR digital filters , 1990, International Conference on Acoustics, Speech, and Signal Processing.

[20]  A. Shah,et al.  A 100 MHz 64-tap FIR digital filter in a 0.8 mu m BiCMOS gate array , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[21]  Jan M. Rabaey,et al.  An integrated CAD system for algorithm-specific IC design , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..