Zero-overhead loop controller that implements multimedia algorithms
暂无分享,去创建一个
[1] David B. Whalley,et al. Effective exploitation of a zero overhead loop buffer , 1999, LCTES '99.
[2] Raminder Singh Bajwa,et al. Instruction buffering to reduce power in processors for signal processing , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[3] Anantha P. Chandrakasan,et al. Low Power Digital CMOS Design , 1995 .
[4] Deependra Talla. Architectural techniques to accelerate multimedia applications on general-purpose processors , 2001 .
[5] John Arends,et al. Instruction fetch energy reduction using loop caches for embedded applications with small tight loops , 1999, ISLPED '99.
[6] Francky Catthoor,et al. Custom Memory Management Methodology , 1998, Springer US.
[7] Ibrahim N. Hajj,et al. Architectural and compiler techniques for energy reduction in high-performance microprocessors , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[8] Lizy Kurian John,et al. Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements , 2003, IEEE Trans. Computers.
[9] Alfred V. Aho,et al. Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.
[10] David A. Patterson,et al. Computer Architecture: A Quantitative Approach , 1969 .
[11] Bruce W. Bomar. Implementation of microprogrammed control in FPGAs , 2002, IEEE Trans. Ind. Electron..
[12] Peter Kuhn,et al. Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation , 1999, Springer US.
[13] Frank Vahid,et al. Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example , 2002, IEEE Computer Architecture Letters.