High-speed low-power multi-threshold double-edge triggered d-type flip-flop

The present invention discloses a high-speed low-power multi-threshold double-edge-triggered D-type flip-flop, comprising: a low-power control circuit for receiving an input signal slp low power control, low-power control input signal is buffered slp respectively, after the output signal: sleep and nsleep; a positive edge triggered latch for receiving a data signal d, the positive phase input clock signal clk, the inverted clock input signal and a signal nclk sleep and nsleep; a positive edge triggered latch data signal d is latched output signal processing qtp; negative edge latch for receiving a data signal d, the positive phase input clock signal clk, the inverted clock input signal and a signal nclk sleep and nsleep; negative edge triggered latch d latched data signal processing output signals: qtn; low power output control circuit for selecting the output value of the positive edge triggered latch or negative edge triggered latch. The present invention has a simple structure, it can improve the transmission efficiency and reduce leakage current and static power consumption.