A Self-Calibrated On-Chip Phase-Noise Measurement Circuit With $-$75 dBc Single-Tone Sensitivity at 100 kHz Offset
暂无分享,去创建一个
[1] K. Nose,et al. A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling , 2006, IEEE Journal of Solid-State Circuits.
[2] Feng Wang,et al. Cascaded PLL design for a 90nm CMOS high performance microprocessor , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[3] L. Franca-Neto,et al. RF System and Circuit Challenges for WiMAX , 2004 .
[4] K. Ichiyama,et al. A programmable on-chip picosecond jitter-measurement circuit without a reference-clock input , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[5] W. P. Robins,et al. Phase Noise in Signal Sources , 1984 .
[6] M. Takamiya,et al. On-chip jitter-spectrum-analyzer for high-speed digital designs , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[7] M. Berroth,et al. Derivation of single-ended CMOS inverter ring oscillator close-in phase noise from basic circuit and device properties , 2004, 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers.
[8] Michiel Steyaert,et al. A 1.5 GHz highly linear CMOS downconversion mixer , 1995, IEEE J. Solid State Circuits.