A compact model of holding voltage for latch-up in epitaxial CMOS
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Yeh-Ning Jou | Chin-Shan Hou | Ming-Jer Chen | Hun-Shung Lee | Jyh-Huei Chen | Pin-Nan Tseng | Ruey-Yun Shiue | Jeng-Kuo Jeng
[1] G.J. Hu,et al. A CMOS Structure with high latchup holding voltage , 1984, IEEE Electron Device Letters.
[2] J.A. Seitchik,et al. An analytic model of holding voltage for latch-up in epitaxial CMOS , 1987, IEEE Electron Device Letters.
[3] Alan G. Lewis,et al. Scaling CMOS Technologies with Constant Latch-Up Immunity , 1986, 1986 Symposium on VLSI Technology. Digest of Technical Papers.