Timed circuit verification using TEL structures

Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In order to automate the process of designing and verifying timed circuits, algorithms for their synthesis and verification are necessary. This paper presents timed event/level (TEL) structures, a specification formalism for timed circuits that corresponds directly to gate-level circuits. It also presents an algorithm based on partially ordered sets to make the state-space exploration of TEL structures more tractable. The combination of the new specification method and algorithm significantly improves efficiency for gate-level timing verification. Results on a number of circuits, including many from the recently published gigahertz unit Test Site (guTS) processor from IBM indicate that modules of significant size can be verified using a level of abstraction that preserves the interesting timing properties of the circuit. Accurate circuit level verification allows the designer to include less margin in the design, which can lead to increased performance.

[1]  Patrice Godefroid.  Using Partial Orders to Improve Automatic Verification Methods , 1990, CAV.

[2]  Alexandre Yakovlev,et al.  Verification of asynchronous circuits using time Petri net unfolding , 1996, DAC '96.

[3]  G. Goossens,et al.  Specification and analysis of timing constraints in signal transition graphs , 1992, [1992] Proceedings The European Conference on Design Automation.

[4]  Bill Lin,et al.  Efficient partial enumeration for timing analysis of asynchronous systems , 1996, DAC '96.

[5]  Chris J. Myers,et al.  Timed Event/Level Structures , 1998 .

[6]  Nevine Nassif,et al.  Timing verification of the 21264: A 600 MHz full-custom microprocessor , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[7]  Rajiv V. Joshi,et al.  A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture , 1991 .

[8]  Kenneth L. McMillan,et al.  Using Unfoldings to Avoid the State Explosion Problem in the Verification of Asynchronous Circuits , 1992, CAV.

[9]  R. Alur.  Techniques for automatic verification of real-time systems , 1991 .

[10]  Antti Valmari,et al.  A stubborn attack on state explosion , 1990, Formal Methods Syst. Des..

[11]  Chris J. Myers,et al.  Verification of Timed Systems Using POSETs , 1998, CAV.

[12]  Jon K. Lexau,et al.  A FIFO ring performance experiment , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[13]  Robert K. Brayton,et al.  STARI: A Case Study in Compositional and Hierarchical Timing Verification , 1997, CAV.

[14]  Henrik Hulgaard.  Timing analysis and verification of timed asynchronous circuits , 1996 .

[15]  S StoneHarold,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973 .

[16]  Trevor N. Mudge,et al.  Timing verification of sequential domino circuits , 1996, Proceedings of International Conference on Computer Aided Design.

[17]  Chris J. Myers,et al.  Computer-aided synthesis and verification of gate-level timed circuits , 1996 .

[18]  Kevin J. Nowka,et al.  Design methodology for a 1.0 GHz microprocessor , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[19]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Eduard Cerny,et al.  Semantics and verification of action diagrams with linear timing , 1998, TODE.

[21]  Teresa H. Y. Meng,et al.  Automatic synthesis of gate-level timed circuits with choice , 1995, Proceedings Sixteenth Conference on Advanced Research in VLSI.

[22]  David L. Dill,et al.  Timing Assumptions and Verification of Finite-State Concurrent Systems , 1989, Automatic Verification Methods for Finite State Systems.

[23]  Chris J. Myers,et al.  Algorithms for synthesis and verification of timed circuits and systems , 1999 .

[24]  Amir Pnueli,et al.  Some Progress in the Symbolic Verification of Timed Automata , 1997, CAV.

[25]  Gaetano Borriello,et al.  Practical applications of an efficient time separation of events algorithm , 1993, ICCAD.

[26]  Stavros Tripakis,et al.  Kronos: A Model-Checking Tool for Real-Time Systems , 1998, CAV.

[27]  Tomohiro Yoneda,et al.  Efficient Verification of Parallel Real–Time Systems , 1993, Formal Methods Syst. Des..

[28]  Mark Russell Greenstreet,et al.  Stari: a technique for high-bandwidth communication , 1993 .

[29]  Rajeev Alur,et al.  Timing Analysis in COSPAN , 1996, Hybrid Systems.

[30]  Zheng Ping Hao.  Specification And Compilation Of Timed Systems , 1998 .

[31]  P. Merlin,et al.  Recoverability of Communication Protocols - Implications of a Theoretical Study , 1976, IEEE Transactions on Communications.

[32]  O. Takahashi,et al.  A 1.0 GHz single-issue 64 b powerPC integer processor , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[33]  J. R. Burch.  Modelling timing assumption with trace theory , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[34]  Trevor N. Mudge,et al.  Timing verification of sequential dynamic circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[35]  Chris J. Myers,et al.  Timed state space exploration using POSETs , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[36]  Teresa H. Y. Meng,et al.  POSET timing and its application to the synthesis and verification of gate-level timed circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[37]  Kevin J. Nowka,et al.  Designing for a gigahertz [guTS integer processor] , 1998, IEEE Micro.

[38]  M. Diaz,et al.  Modeling and Verification of Time Dependent Systems Using Time Petri Nets , 1991, IEEE Trans. Software Eng..

[39]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[40]  Wang Yi,et al.  Partial Order Reductions for Timed Systems , 1998, CONCUR.

[41]  Ran Ginosar,et al.  RAPPID: an asynchronous instruction length decoder , 1999, Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[42]  Vinod Narayanan,et al.  Static timing analysis for self resetting circuits , 1996, Proceedings of International Conference on Computer Aided Design.

[43]  Tomohiro Yoneda,et al.  Timed trace theoretic verification using partial order reduction , 1999, Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[44]  Kevin J. Nowka,et al.  Circuit design techniques for a gigahertz integer microprocessor , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[45]  Chris J. Myers,et al.  Automatic Verification of Timed Circuits , 1994, CAV.