Optimized Selection of Frequencies for Faster-Than-at-Speed Test

Small gate delay faults (SDFs) are not detectable at-speed, if they can only be propagated along short paths. These hidden delay faults (HDFs) do not influence the circuit's behavior initially, but they may indicate design marginalities leading to early-life failures, and therefore they cannot be neglected. HDFs can be detected by faster-than-at-speed test (FAST), where typically several different frequencies are used to maximize the coverage. A given set of test patterns P potentially detects a HDF if it contains a test pattern sensitizing a path through the fault site, and the efficiency of FAST can be measured as the ratio of actually detected HDFs to potentially detected HDFs. The paper at hand targets maximum test efficiency with a minimum number of frequencies. The procedure starts with a test set for transition delay faults and a set of preselected equidistant frequencies. Timing-accurate simulation of this initial setup identifies the hard-to-detect faults, which are then targeted by a more complex timing-aware ATPG procedure. For the yet undetected HDFs, a minimum number of frequencies are determined using an efficient hypergraph algorithm. Experimental results show that with this approach, the number of test frequencies required for maximum test efficiency can be reduced considerably. Furthermore, test set inflation is limited as timing-aware ATPG is only used for a small subset of HDFs.

[1]  Haihua Yan,et al.  Experiments in detecting delay faults using multiple higher frequency clocks and results from neighboring die , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[2]  Chang Liu,et al.  FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects , 2014, 2014 International Test Conference.

[3]  Rolf Drechsler,et al.  As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization , 2011, 2011 Design, Automation & Test in Europe.

[4]  Edward J. McCluskey,et al.  Failing Frequency Signature Analysis , 2008, 2008 IEEE International Test Conference.

[5]  Ananta K. Majhi,et al.  On hazard-free patterns for fine-delay fault testing , 2004 .

[6]  Bernd Becker,et al.  Early-life-failure detection using SAT-based ATPG , 2013, 2013 IEEE International Test Conference (ITC).

[7]  Lei Shi,et al.  An Exact Fast Algorithm for Minimum Hitting Set , 2010, 2010 Third International Joint Conference on Computational Science and Optimization.

[8]  Mark Mohammad Tehranipoor,et al.  Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Huawei Li,et al.  Testable Path Selection and Grouping for Faster Than At-Speed Testing , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Teresa L. McLaurin,et al.  The testability features of the MCF5407 containing the 4th generation ColdFire(R) microprocessor core , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[11]  Hyunki Kim,et al.  Low-cost gate-oxide early-life failure detection in robust systems , 2010, 2010 Symposium on VLSI Circuits.

[12]  Xiaoqing Wen,et al.  GPU-accelerated small delay fault simulation , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[13]  J. Boyer.  Easily Implement PLL Clock Switching for At-Speed Test By taking advantage of pattern-generation features , a simple logic design can utilize phase-locked-loop clocks for accurate at-speed testing , .

[14]  Songwei Pei,et al.  An on-chip clock generation scheme for faster-than-at-speed delay testing , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[15]  Jinjun Xiong,et al.  Statistical path selection for at-speed test , 2008, ICCAD 2008.

[16]  Jacob A. Abraham,et al.  On-chip Programmable Capture for Accurate Path Delay Test and Characterization , 2008, 2008 IEEE International Test Conference.

[17]  N. Ahmed,et al.  A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-drop Effects , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[18]  Chen Wang,et al.  Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects , 2006, 2006 15th Asian Test Symposium.

[19]  Hideo Fujiwara,et al.  Faster-than-at-speed test for increased test quality and in-field reliability , 2011, 2011 IEEE International Test Conference.