A flexible redundancy technique for high-density DRAMs

The limitations of conventional redundancy techniques are pointed out and a novel redundancy technique is proposed for high-density DRAMs using multidivided data-line structures. The proposed technique features a flexible relationship between spare lines and spare decoders, as well as lower probability of unsuccessful repair. With this technique the yield improvement factor of 64-Mb DRAMs and beyond is estimated to be more than twice that with the conventional technique in the early stages of production. >

[1]  R.P. Cenker,et al.  A fault-tolerant 64K dynamic random-access memory , 1979, IEEE Transactions on Electron Devices.

[2]  Katsuhiro Shimohigashi,et al.  Redundancy Techniques for Dynamic RAMs , 1982 .

[3]  C. H. Stapper,et al.  On yield, fault distributions, and clustering of particles , 1986 .

[4]  M. Wada,et al.  A redundancy circuit for a fault-tolerant 256K MOS RAM , 1982, IEEE Journal of Solid-State Circuits.

[5]  R. Hori,et al.  An experimental 1 Mbit DRAM based on high S/N design , 1984, IEEE Journal of Solid-State Circuits.

[6]  S. E. Schuster Multiple word/bit line redundancy for semiconductor memories , 1978 .

[7]  R. G. Nelson,et al.  Laser programmable redundancy and yield improvement in a 64K DRAM , 1981 .

[8]  K. Itoh Trends in megabit DRAM circuit design , 1989, International Symposium on VLSI Technology, Systems and Applications,.

[9]  P. Sharp,et al.  Redundancy techniques for fast static RAMs , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.