Towards an integrated line edge roughness understanding: metrology, characterization, and plasma etching transfer
暂无分享,去创建一个
Evangelos Gogolides | Vassilios Constantoudis | George Kokkoris | E. Gogolides | V. Constantoudis | G. Kokkoris
[1] Evangelos Gogolides,et al. Line edge roughness transfer during plasma etching: modeling approaches and comparison with experimental results , 2009, Advanced Lithography.
[2] Atsuko Yamaguchi,et al. Bias-free measurement of LER/LWR with low damage by CD-SEM , 2006, SPIE Advanced Lithography.
[3] J. Foucher,et al. Impact of acid diffusion length on resist LER and LWR measured by CD-AFM and CD-SEM , 2007, SPIE Advanced Lithography.
[4] J. S. Villarrubia,et al. Unbiased estimation of linewidth roughness , 2005, SPIE Advanced Lithography.
[5] M. Ercken,et al. Full spectral analysis of line width roughness , 2005, SPIE Advanced Lithography.
[6] Tomoki Inoue,et al. Striations on Si Trench Sidewalls Observed by Atomic Force Microscopy , 1997 .
[7] E. Gogolides,et al. Nanoscale Roughness Effects at the Interface of Lithography and Plasma Etching: Modeling of Line-Edge-Roughness Transfer During Plasma Etching , 2009, IEEE Transactions on Plasma Science.
[8] R. Rooyackers,et al. Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield , 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..
[9] Atsuko Yamaguchi,et al. Metrology of LER: influence of line-edge roughness (LER) on transistor performance , 2004, SPIE Advanced Lithography.
[10] Atsuko Yamaguchi,et al. Characterization of line-edge roughness in resist patterns and estimations of its effect on device performance , 2003, SPIE Advanced Lithography.
[11] Wen-li Wu,et al. Linewidth roughness and cross-sectional measurements of sub-50 nm structures with CD-SAXS and CD-SEM , 2008, SPIE Advanced Lithography.
[12] Philippe Foubert,et al. Impact of post-litho linewidth roughness smoothing processes on the post-etch patterning result , 2011 .
[13] John S. Villarrubia,et al. Determination of optimal parameters for CD-SEM measurement of line-edge roughness , 2004, SPIE Advanced Lithography.
[14] E. Gogolides,et al. Effects of resist sidewall morphology on line-edge roughness reduction and transfer during etching: is the resist sidewall after development isotropic or anisotropic? , 2010 .
[15] Benjamin Bunday,et al. LER detection using dark field spectroscopic reflectometry , 2010, Advanced Lithography.
[16] Olivier Joubert,et al. Unbiased line width roughness measurements with critical dimension scanning electron microscopy and critical dimension atomic force microscopy , 2012 .
[17] Seiichi Kondo,et al. Mechanism of reducing line edge roughness in ArF photoresist by using CF3I plasma , 2009 .
[18] C Millar,et al. Understanding LER-Induced MOSFET $V_{T}$ Variability—Part II: Reconstructing the Distribution , 2010, IEEE Transactions on Electron Devices.
[19] James A. Sethian,et al. The Fast Construction of Extension Velocities in Level Set Methods , 1999 .
[20] M. Ieong,et al. Modeling line edge roughness effects in sub 100 nanometer gate length devices , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).
[21] Harry J. Levinson,et al. The transfer of photoresist LER through etch , 2006, SPIE Advanced Lithography.
[22] Atsushi Hiraiwa,et al. Discrete power spectrum of line width roughness , 2009 .
[23] Evangelos Gogolides,et al. Characterization and modeling of line width roughness (LWR) , 2005, SPIE Advanced Lithography.
[24] Abdelkarim Mercha,et al. Impact of line width roughness on device performance , 2006, SPIE Advanced Lithography.
[25] F. Cerrina,et al. Process dependence of roughness in a positive-tone chemically amplified resist , 1998 .
[26] Evangelos Gogolides,et al. 3d modeling of LER transfer from the resist to the underlying substrate: the effect of the resist roughness , 2012, Advanced Lithography.
[27] Olivier Joubert,et al. Plasma impact on 193 nm photoresist linewidth roughness: Role of plasma vacuum ultraviolet light , 2009 .
[28] Costas J. Spanos,et al. Robust estimation of line width roughness parameters , 2010 .
[29] Olivier Joubert,et al. Linewidth roughness transfer measured by critical dimension atomic force microscopy during plasma patterning of polysilicon gate transistors , 2008 .
[30] Ronald G. Dixson,et al. Generalized ellipsometry of artificially designed line width roughness , 2011 .
[31] J. A. Sethian,et al. Fast Marching Methods , 1999, SIAM Rev..
[32] Gregg M. Gallatin,et al. Effect of thin-film imaging on line edge roughness transfer to underlayers during etch processes , 2004 .
[33] Kouichirou Tsujita,et al. Influence of line-edge roughness on MOSFET devices with sub-50-nm gates , 2004, SPIE Advanced Lithography.
[34] Hyun-Woo Kim,et al. Experimental investigation of the impact of LWR on sub-100-nm device performance , 2004, IEEE Transactions on Electron Devices.
[35] S. J. Pearton,et al. Reduction of sidewall roughness during dry etching of SiO2 , 1992 .
[36] Wolfgang Osten,et al. Fieldstitching with Kirchhoff-boundaries as a model based description for line edge roughness (LER) in scatterometry , 2009 .
[37] E. Gogolides,et al. A review of line edge roughness and surface nanotexture resulting from patterning processes , 2006 .
[38] A. Yamaguchi,et al. Characterization of line edge roughness in resist patterns by Fourier analysis and auto-correlation function , 2002, 2002 International Microprocesses and Nanotechnology Conference, 2002. Digest of Papers..
[39] A. Asenov,et al. Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness , 2003 .
[40] George P. Patsis,et al. Integrated simulation of line-edge roughness (LER) effects on sub-65nm transistor operation: From lithography simulation, to LER metrology, to device operation , 2006, SPIE Advanced Lithography.
[41] E. Gogolides,et al. Line edge roughness and critical dimension variation: Fractal characterization and comparison using model functions , 2004 .
[42] Harry J. Levinson,et al. Line-edge roughness in 193-nm resists: lithographic aspects and etch transfer , 2007, SPIE Advanced Lithography.
[43] D Reid,et al. Understanding LER-Induced MOSFET $V_{T}$ Variability—Part I: Three-Dimensional Simulation of Large Statistical Samples , 2010, IEEE Transactions on Electron Devices.
[44] Evangelos Gogolides,et al. Photoresist line-edge roughness analysis using scaling concepts , 2003, SPIE Advanced Lithography.
[45] Ndubuisi G. Orji,et al. Line edge roughness metrology using atomic force microscopes , 2005 .
[46] V. Constantoudis,et al. Fractal dimension of line width roughness and its effects on transistor performance , 2008, SPIE Advanced Lithography.
[47] C.H. Diaz,et al. An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling , 2001, IEEE Electron Device Letters.
[48] Costas Spanos,et al. Impact of gate line edge roughness on double-gate FinFET performance variability , 2008, SPIE Advanced Lithography.
[49] Atsuko Yamaguchi,et al. Influence of image processing on line-edge roughness in CD-SEM measurement , 2008, SPIE Advanced Lithography.
[50] Yi-Sha Ku,et al. Angular scatterometry for line-width roughness measurement , 2007, SPIE Advanced Lithography.
[51] Γεώργιος Πάτσης,et al. Modeling of line edge roughness transfer during plasma etching , 2015 .
[52] D. Graves,et al. Plasma-polymer interactions: A review of progress in understanding polymer resist mask durability during plasma etching for nanoscale fabrication , 2011 .
[53] J.C.S. Woo,et al. TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling , 2004, IEEE Transactions on Semiconductor Manufacturing.
[54] Evangelos Gogolides,et al. Correlation length and the problem of line width roughness , 2007, SPIE Advanced Lithography.
[55] John S. Villarrubia,et al. Issues in Line Edge and Linewidth Roughness Metrology , 2005 .
[56] Angeliki Tserepi,et al. Quantification of line-edge roughness of photoresists. II. Scaling and fractal analysis and the best roughness descriptors , 2003 .
[57] Angeliki Tserepi,et al. Quantification of line-edge roughness of photoresists. I. A comparison between off-line and on-line analysis of top-down scanning electron microscopy images , 2003 .
[58] H. Sawin,et al. Review of profile and roughening simulation in microelectronics plasma etching , 2009 .
[59] Olivier Joubert,et al. Plasma treatments to improve line-width roughness during gate patterning , 2013 .
[60] Kenji Yamazaki,et al. Influence of edge roughness in resist patterns on etched patterns , 1998 .
[61] Vassilios Constantoudis,et al. Evaluation of methods for noise-free measurement of LER/LWR using synthesized CD-SEM images , 2013, Advanced Lithography.