Design and implementation of double precision floating point division and square root on FPGAs

This paper presents the sequential and pipelined designs of a double precision floating point divider and square root unit. The pipelining of these units is based on partial and full unrolling of the iterations in low-radix digit recurrence algorithms. These units are synthesized to produce common-denominator implementations that can be mapped on any FPGA chip regardless of architectural differences between the chips. The implementations of these designs show that their performances are comparable to, and sometimes higher than, the performances of non-iterative designs based on high radix numbers. While the iterative divider and square root unit occupy less than 1% of an XC2V6000 FPGA chip, their pipelined counterparts can produce throughputs that reach the 100 MFLOPS mark by consuming a modest 8% of the chip area. The pipelining of these iterative designs target high throughput computations encountered in some space applications

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