Architectural tradeoffs in the design of VLSI-based associative memories

Abstract Associative memories and algorithms for performing various operations on them have been studied extensively over the past three decades. Speedup analyses offered for such algorithms are based on the assumption of a fixed cycle time for the associative memory, independent of size. Whereas this is acceptable for small capacities which have been practical in the past, the potential for realizing extremelyy large systems by exploiting advances in the VLSI technology necessitates a reexamination of the above premise. In this paper, we offer systolic designs for associative memories whose cyclestimes are realistically constant and independent of their size. The designs are based on well-known principles of pipelining and systolic operation using small building-block associative memories. Several alternative organizations, from a simple linear array to higher-dimensional meshes and trees are examined and evaluated with respect to cost, throughput, and response latency.

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