A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2nd-Order Noise Shaping in 65nm CMOS Technology

[1]  Franco Maloberti,et al.  A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[2]  Ian Galton,et al.  A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC , 2010, IEEE Journal of Solid-State Circuits.

[3]  Akira Matsuzawa,et al.  A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[4]  Y. Makino,et al.  An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering , 2003, IEEE J. Solid State Circuits.

[5]  Kenichi Okada,et al.  14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[6]  Ian Galton,et al.  Gain error correction technique for pipelined analogue-to-digital converters , 2000 .

[7]  Tomohito Terasawa,et al.  A 0.0027-mm2 9.5-bit 50-MS/s all-digital A/D converter TAD in 65-nm digital CMOS , 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

[8]  Jaewook Kim,et al.  Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Amr Elshazly,et al.  A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer , 2012, IEEE Journal of Solid-State Circuits.

[10]  A. K. Gupta,et al.  A Two-Stage ADC Architecture With VCO-Based Second Stage , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Han Yan,et al.  A 1.5 mW 68 dB SNDR 80 Ms/s 2 $\times$ Interleaved Pipelined SAR ADC in 28 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.

[12]  Sudhakar Pamarti,et al.  Linearization Through Dithering: A 50 MHz Bandwidth, 10-b ENOB, 8.2 mW VCO-Based ADC , 2015, IEEE Journal of Solid-State Circuits.

[13]  Willy M. C. Sansen,et al.  1.3 Analog CMOS from 5 micrometer to 5 nanometer , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[14]  M.Z. Straayer,et al.  A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer , 2008, IEEE Journal of Solid-State Circuits.

[15]  Nan Sun,et al.  A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping , 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

[16]  Peng Gao,et al.  A 40MHz-BW two-step open-loop VCO-based ADC with 42fJ/step FoM in 40nm CMOS , 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

[17]  Pavan Kumar Hanumolu,et al.  A 12.5-bit 4 MHz 13.8 mW MASH $\Delta \Sigma$ Modulator With Multirated VCO-Based ADC , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.