A 24-Gb/s Double-Sampling Receiver for Ultra-Low-Power Optical Communication

This paper describes a dense, high-speed, and low-power CMOS optical receiver implemented in a 65-nm CMOS technology. High data rate is achieved using an RC double-sampling front-end and a novel dynamic offset-modulation technique. The low-voltage double-sampling technique provides high power efficiency by avoiding linear high-gain elements conventionally employed in transimpedance-amplifier (TIA) receivers. In addition, the demultiplexed output of the receiver helps save power in the following digital blocks. The receiver functionality was validated by electrical and optical measurements. The receiver achieves up to 24 Gb/s data rate with better than 160-μA current sensitivity in an experiment performed by a photodiode current emulator embedded on-chip. Optical measurements performed by a 1550-nm wire-bonded photodiode show better than - 4.7-dBm optical sensitivity at 24 Gb/s. The receiver offers peak power efficiency of 0.36 pJ/b at 20 Gb/s from a 1.2-V supply and occupies less than 0.0028 mm2 silicon area.

[1]  Richard T. Witek,et al.  A 160 MHz 32 b 0.5 W CMOS RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[2]  T Takemoto,et al.  A Compact 4$\, \times \,$25-Gb/s 3.0 mW/Gb/s CMOS-Based Optical Receiver for Board-to-Board Interconnects , 2010, Journal of Lightwave Technology.

[3]  F. Ellinger,et al.  A 100-mW 4/spl times/10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects , 2005, IEEE Journal of Solid-State Circuits.

[4]  Stefanos Sidiropoulos,et al.  A semidigital dual delay-locked loop , 1997 .

[5]  Ashok V. Krishnamoorthy,et al.  10 Gbps, 530 fJ/b optical transceiver circuits in 40 nm CMOS , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[6]  Samuel Palermo,et al.  Optical I/O technology for tera-scale computing , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[7]  A. Emami-Neyestanak,et al.  A 1.6 Gb/s, 3 mW CMOS receiver for optical communication , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[8]  Azita Emami-Neyestanak,et al.  A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects , 2008, IEEE Journal of Solid-State Circuits.

[9]  A. Emami-Neyestanak,et al.  CMOS transceiver with baud rate clock recovery for optical interconnects , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[10]  W.J. Dally,et al.  Low-power area-efficient high-speed I/O circuit techniques , 2000, IEEE Journal of Solid-State Circuits.

[11]  C.L. Schow,et al.  Low-Power 16 x 10 Gb/s Bi-Directional Single Chip CMOS Optical Transceivers Operating at ≪ 5 mW/Gb/s/link , 2009, IEEE Journal of Solid-State Circuits.

[12]  A. Emami-Neyestanak,et al.  Ultra low-power receiver design for dense optical interconnects , 2012, 2012 Optical Interconnects Conference.

[13]  Marcel J. M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[14]  Dan Song,et al.  A Fully Integrated 4 $\times$ 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 $\mu{\hbox {m}}$ CMOS SOI Technology , 2006, IEEE Journal of Solid-State Circuits.

[15]  Vladimir Stojanovic,et al.  A monolithically-integrated optical receiver in standard 45-nm SOI , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

[16]  Azita Emami-Neyestanak,et al.  An 18.6Gb/s double-sampling receiver in 65nm CMOS for ultra-low-power optical communication , 2012, 2012 IEEE International Solid-State Circuits Conference.

[17]  Byungsub Kim,et al.  A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[18]  Meisam Honarvar Nazari,et al.  A 15Gb/s 0.5mW/Gb/s 2-tap DFE receiver with far-end crosstalk cancellation , 2011, 2011 IEEE International Solid-State Circuits Conference.

[19]  J.D.H. Alexander.  Clock recovery from random binary signals , 1975 .