A low-power design methodology for sigma-delta modulators with relaxation of required circuit specifications

A design methodology of high-order sigma-delta modulators (SDMs) with relaxation of required circuit specifications is proposed to reduce the required power consumption and to be suitable for the nano-scale circuit. According to the proposed design flow, more relaxed circuit specifications can be selected so that designers can maintain system performance. One design example is employed to verify the proposed design flow. Circuit-level simulation reveals that the power consumption is lower under the same system performance compared with a conventional design flow. The circuits are implement with TSMC 90nm 1P9M CMOS process and the measured signal-to-noise distortion ratio (SNDR) is 64.5 dB, with a power consumption of 303μW.

[1]  Yves Rolain,et al.  Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS , 2010, IEEE Journal of Solid-State Circuits.

[2]  Youngcheol Chae,et al.  Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator , 2009, IEEE J. Solid State Circuits.

[3]  Jan M. Rabaey,et al.  MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[4]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[5]  Andrea Baschirotto,et al.  Behavioral modeling of switched-capacitor sigma-delta modulators , 2003 .

[6]  W. Sansen,et al.  A 3.3 V 15-bit delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL-applications , 1999, Proceedings of the 24th European Solid-State Circuits Conference.

[7]  Francisco V. Fernández,et al.  High-Level Synthesis of Switched-Capacitor , Switched-Current and Continuous-Time Modulators Using SIMULINK-Based Time-Domain Behavioral Models , 2005 .

[8]  G. Temes.  Delta-sigma data converters , 1994 .

[9]  Andreas Demosthenous,et al.  Constant-Resistance CMOS Input Sampling Switch for GSM/WCDMA High Dynamic Range $\Delta \Sigma$ Modulators , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Tai-Haur Kuo,et al.  Automatic coefficients design for high-order sigma-delta modulators , 1999 .

[11]  Michiel Steyaert,et al.  Design of Multi-Bit Delta-SIGMA A/D Converters , 2002 .

[12]  Ángel Rodríguez-Vázquez,et al.  High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Bruce A. Wooley,et al.  A third-order sigma-delta modulator with extended dynamic range , 1994 .