A Built-In Test Circuit for Detecting Open Defects by IDDT Appearance Time in CMOS ICs

A built-in test circuit is proposed to detect an open defect in a CMOS IC by means of appearance time of dynamic supply current of the IC. A layout of an IC embedding the test circuit is designed. It is shown by Spice simulation that an open defect in the IC can be detected with the test circuit.

[1]  R. G. Bennetts,et al.  Defect-Oriented Testing , 1995 .

[2]  Robert C Aitken.  Defect-Orinted Testing , 2006 .

[3]  Masaki Hashizume,et al.  CMOS open fault detection by appearance time of switching supply current , 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

[4]  Dong Sam Ha,et al.  IDDT Testing: An Efficient Method for Detecting Delay Faults and Open Defects * , 2001 .

[5]  Ayman I. Kayssi,et al.  The effectiveness of delay and IDDT tests in detecting resistive open defects for nanometer CMOS adder circuits , 2011, 2011 IEEE 6th International Design and Test Workshop (IDT).

[6]  J. Ramirez-Angulo,et al.  A high-speed dynamic current sensor for iDD test based on the flipped voltage follower , 2003, Southwest Symposium on Mixed-Signal Design, 2003..